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Reconfigurable and High Performance Computing Lab INAOE Puebla, Mexico Embedded vision with FPGA vs CUDA processing. Directions and platform proposal WASC 2014 20 June 2014 Dr. Miguel Arias Estrada ariasmo@inaoep.mx Content

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Embedded vision with FPGA vs CUDA processing. Directions and platform proposal

WASC 2014 20 June 2014

Dr. Miguel Arias Estrada

ariasmo@inaoep.mx

Reconfigurable and High Performance Computing Lab INAOE – Puebla, Mexico

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Content

1. Introduction

2. Previous work on FPGA architectures

3. FPGA cameras

4. Platform proposal: FPGA vs CUDA

5. Long term project

6. Conclusions

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Reconfigurable and High Performance Computing Laboratory

l Computer Science

Department

n 4 Researchers n 10+ M.Sc. Students n 5+ Ph.D. Students

l Active since1998 l Research on:

n Real time computer vision n Criptography and Cipher n Hardware Signal

Processing

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1. Introduction

Smart camera approach High performance low level vision computing at camera 3D Vision, tracking / surveillance applications

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2. Previous work on FPGA

architectures

Edge / Corner Detection Stereo disparity Target Tracking Motion correlation and Optical Flow 3D from Optical Flow SIFT / SURF / LISF feature detection

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Approach

l Off-the-shelf development boards l Focus on FPGA architecture.

Application can be built in parallel

l Goal: Reach video rate processing

(i.e. 30 fps)

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Edge and corner detection

Industrial applications Basis for other image processing applications

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Edge and corner detection architecture

COR COR

COR

COR COR

COR

N N

M N

M U X

P O S T

R A M 2 Address Generator

Decodificador

R A M 1 N N

M N

COR

N-1

COR

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Demostration with RC200

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Target processor

FPGA implementation

REGISDTRO (HEADER) VEN TANA P AT RÓN VEN TANA D E BÚSQUEDA

PRO CESADO R DE CORRELACIÓN

Target tracking

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Multiple object tracking

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Performance gain

Algorithm acceleration

25 x to 50x compared to PC computer

Drawback

Modularity and reuse Lack of standards for vision cores

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3. FPGA based cameras

Overview of : Early concept Current approaches

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Smart camera architecture

Imager L

FPGA Host Computer Smart camera

High BW channel (Ethernet or USB2.0) Reconfigurable processor

Soft processor (ctrl)
Parallel processor
I/O and device interfaces

One or two (stereo) imagers Memory Comm Imager R

Image and inter- mediate data buffer

High level processor (PC or robot CPU)

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FPGA camera

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Custom Spartan6 development board

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FPGA ¡camera ¡– ¡2012/2013 ¡

USB 3.0 5 Megapixeles Spartan 6 device FPGA for sensor control and data packaging FPGA room for additional processing

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FPGA ¡camera ¡prototype

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4. Platform proposal

Current work FPGA/Arm platform + Camera Tegra K1 platform + Camera

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4.1 FPGA based Proposal

l Use of a SoC (System on a Chip) l FPGA + ARM processor + Embedded

Linux

l Xilinx Zynq7000 + support electronics l Reconfiguration + I/O flexibility

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FPGA platform

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FPGA Platform :: MicroZed

l Xilinx XC7Z010 l USB 2.0 l Gbit Ethernet l 1 Gbyte SRAM DDR3 l 128 Mb Flash l Micro SD card l 100 I/O l Embedded Linux

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4.2 CUDA platform

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DRAM

Cache ALU Control ALU ALU ALU

DRAM

CPU GPU

CPU vs GPU

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CUDA programming

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FPGA vs Embedded CUDA

FPGA CUDA

Advantages

Low power
High performance
Small size, possible

to migrate to VLSI

Easy to program
Speed up
Floating point

Inconvenient

Complex to

implement

Long to learn
Architecture

complexity vs speedup

Reformulate in

parallel: core + memory use

Power consumption

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5. Long term project

l Image + Feature extraction in Camera l Form descriptor extraction at the camera level

(best for CUDA programing)

l Host computer or Cloud for high level

cognitive modeling / BigData techniques

l Network of cameras can open new research

possibilities

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PARTIAL CORRESPONDENCE OF FORM

Object recognition using form
From a given object model, select a subset of

corresponding edge segments.

Clasificación de objetos en imágenes usando características de forma

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PARTIAL CORRESPONDENCE OF FORM

Part of the contour can be connected incorrectly with the background or other object, giving a wrong edge to be matched

Clasificación de objetos en imágenes usando características de forma

CHALLENGE ¡

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Open contour
Self-contained
Rotation and translation invariant

OCTAR FORM DESCRIPTOR

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PARTIAL CORRESPONDENCE OF FORM

FORM ¡DESCRIPTOR ¡

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Clasificación de objetos en imágenes usando características de forma

PARTIAL CORRESPONDENCE OF FORM

OBJECT ¡LOCATION ¡

Each partial

correspondence vote for the center of the

bject

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Clasificación de objetos en imágenes usando características de forma

OBJECT ¡LOCATION ¡

Fragments that can

be part of the object

PARTIAL CORRESPONDENCE OF FORM

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6. Conclusions

l FPGA based processing for low level feature

extraction

l Form descriptors and medium level processing is

better with CUDA based platform

l Potential to combine networks of cameras with

embedded vision processing and Cloud computing

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