Performance and Design Considerations for Gate-All-around - PowerPoint PPT Presentation

Performance and Design Considerations for Gate-All-around Stacked-NanoWires FETs S. Barraud, V. Lapras, B. Previtali, M.P. Samson, J. Lacord, S. Martinie, M.-A. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J.M. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J.C. Barbé, M. Vinet, and T. Ernst CEA-LETI, Minatec Campus, Grenoble, France STMicroelectronics, Crolles, France

Context of this work Two main MOSFET architectures for advanced CMOS ? 14nm SAMSUNG 3D FinFET 14nm INTEL 22nm INTEL 16nm TSMC New MOSFET architectures need to be proposed 22nm GF 28nm ST Back-gate control using thin BOX capacitive 2D FDSOI Single-gate  reduction of SCE controlled by thinner T Si or T BOX 2.

Context of this work Plenty of space … at the top ! Max M. Shulaker et al., Nature 2017, Stanford 3.

2017 press releases May │ 2017 Samsung set to lead the future of foundry with comprehensive process roadmap down to 4nm 4LPP (4nm Low Power Plus): 4LPP will be the first implementation of next generation device architecture – MBCFET TM structure (Multi Bridge Channel FET). MBCFET TM is Samsung’s unique GAAFET ( Gate All Around FET ) technology that uses a Nanosheet device to overcome the physical scaling and performance limitations of the FinFET architecture. https://news.samsung.com/global/samsung-set-to-lead-the-future-of-foundry-with- comprehensive-process-roadmap-down-to-4nm June │ 2017 IBM claims 5nm Nanosheet breakthough IBM researchers and their partners have developed a new transistor architecture based on Stacked Silicon Nanosheets that they believe will make FinFETs obsolete at the 5nm node http://www.eetimes.com/document.asp?doc_id=1331850& GAA MOSFET devices are becoming an industrial reality 4.

3D stacked structures 15 years of innovation Internal spacers High density Nanowires with introduction MultiBridge independent Channel gates MOSFET S.Y. Lee et al SAMSUNG IEEE Trans Nano 2003 E. Bernard et al. VLSI 08 LETI - STM IBM ONO N. Loubet & al. (VLSI 2017) 13 crystalline crystalline First Stacked levels ! Strain 3D Flash NW CMOS booster 10 -4 V D =50mV L=550nm In-plane deformation V G2 =0.8 to -1.4V e xx 10 -6 step = -0.2V Drain Current I D (A) Si 0.7 Ge 0.3 4T-  FET Si 0.7 Ge 0.3 3T-  FET V S 10 -8 e 4T-FET SS=82mV/dec. Si 0.7 Ge 0.3 Si 0.7 Ge 0.3 Si channel SS=62mV/dec. V G1 V G2 b Out-of-plane deformation 10 -10 e yy 3T-FET V D Si 0.7 Ge 0.3 Si channel Si 0.7 Ge 0.3 10 -12 V G e Inner spacer V D T. Ernst et al. , 10 -14 -1 -0.5 0 0.5 1 1.5 2 IEDM06 Gate 1 voltage V G1 (V) S. Barraud et al. C. Dupré et al. LETI IEDM 2016 A. Hubert et al. IEDM 2008 T. Ernst et al. 5. IEDM 2008 -LETI Micro. Eng. 2011

From FinFet to stacked NW Fin FETs GAA Wire FETs Same process (LETI 2008 – IEDM) TCAD FinFET 60 14nm INTEL [1] IMEC [2] W=7nm, H Fin =45nm DIBL (mV/V) L G =10nm 40 GAA 7nm 20 10 15 20 25 30 35 40 [1] S. Natarajan et al. , IEDM, 2014. Gate length (nm) [2] H. Mertens et al. , VLSI Technology, 2016. 6.

Motivation/Objective CPP Device architecture scaling CPP scaling Layout FP L G reduction Footprint Energy per switch, fJ (LF) Electrostatic booster to keep low Metal leakage current Gate Alternative Fins options: GAA structures Contact • Increase I eff per footprint • Decrease C eq per footprint 3 Fins Switching delay, ps C PARASITICS ELECTROSTATICS MOBILITY Device Fabrication FF/NW/NS FF/NW/NS FF/NW/NS FF/NW/NS 7.

Outline • Performance/Design consideration • Device Fabrication – Inner spacer – SiGe S/D • Strain Characterization – Precession Electron Diffraction • Perspectives • Summary and Conclusion 8.

FinFET Layout footprint (nm) NW FF W=7nm H Fin =43nm Layout footprint (nm) FF 120 Footprint (nm) 80 40 TCAD 0,2 0,4 0,6 0,8 W eff (µm) W eff =circonference of Fin (2H Fin +W) 9.

FinFET to GAA Nanowires Layout footprint (nm) NW NW FF W=7nm H Fin =43nm Layout footprint (nm) FF 120 Footprint (nm) -14% ? 80 40 TCAD 0,2 0,4 0,6 0,8 W eff (µm) W eff =circonference of Fin (2H Fin +W) 10.

GAA Nanowires to Nanosheets W=82nm W NS NW 132nm NS +5% w eff 120 Footprint (nm) FF 107nm 82nm W=32nm 80 57nm +24% w eff 32nm 40 x3GAA W=15nm 0,2 0,4 0,6 0,8 +42% w eff W eff (µm) W eff =circonference of Fin (2H Fin +W) 11.

Short-channel effects Electrostatics of multi-gates MOSFET transistors 60 FinFET (H Fin =43nm, W=7nm) 1 st boundary condition 50 DIBL (mV/V) 40 30 TCAD (L G =16nm) 0 20 40 60 80 100 120 140 W NS (nm) 12.

Short-channel effects Electrostatics of multi-gates MOSFET transistors 60 FinFET (H Fin =43nm, W=7nm) 1 st boundary condition 50 DIBL (mV/V) 40 30 TCAD (L G =16nm) NW 2 nd boundary condition 0 20 40 60 80 100 120 140 W NS (nm) • Strong reduction of DIBL for Gate -all-around nanowire. → O ptimal electrostatics control! 13.

Short-channel effects Electrostatics of multi-gates MOSFET transistors 60 FinFET (H Fin =43nm, W=7nm) 1 st boundary condition 50 DIBL (mV/V) 40 30 TCAD (L G =16nm) NW 2 nd boundary condition 0 20 40 60 80 100 120 140 W NS (nm) • GAA Nanosheets (thin and wide wires) show intermediate DIBL between NW and FinFET. DIBL depends on wire width (W). 14.

Tradeoff between SCE and W eff 60 60 60 FF FF FF FF 50 50 50 DIBL (mV/V) DIBL (mV/V) DIBL (mV/V) 40 40 40 NW 30 30 30 L G =13nm L G =13nm L G =13nm LF=57nm NW NW LF=82nm LF=107nm NW 20 20 20 0,2 0,4 0,4 0,6 0,4 0,6 W eff (µm) W eff (µm) W eff (µm) NS • GAA stacked -nanosheets maximize W eff (drive current) per layout footprint with improved channel electrostatics. 15.

Power/Perf. Optimization FP=25nm FF 0 10 3 stacked GAA HP L G =16nm Normalized I OFF 32nm H NW =6.5nm 57nm 19.5nm 24nm -1 13nm 10 15nm LF=57nm LP LF=82nm LF=107nm W=7nm -2 10 0,5 1,0 1,5 Normalized I ON GAA Nanosheet transistors offers more freedom to designers for the power-performance optimization thanks to a fine tuning of the device width. 16.

Parasitic capacitances and delay t : Delay I eff : Effective drive current I eff =(I H +I L )/2 FF NW I H =I DS (V GS =V DD , V DS =V DD /2) I L =I DS (V GS =V DD /2, V DS =V DD ) Supply voltage V DD =0.7V FO=3 L G =16nm Spacer size: 4.2nm EOT=0.67nm C back-end =2fF M=2: Miller effect in inverter 20 LF=82nm (4 Fins with FP=25nm) LF=57nm (3 Fins with FP=25nm) C eq is reduced for NWs (W=7nm) 82nm 10 C eq (%) but no delay reduction is achieved, 32nm while performance can be 15.3nm 57nm 0 significantly improved for 19.5nm nanosheet design having wider NW C eq (%) (W=7nm) wires. A delay reduction of around -10 20% is expected for W NS ~30nm -40 -20 0 20 40 t p t p (%) (%) 17.

Number of Stacked-GAA NS H Fin =29nm H Fin =72nm H Fin =115nm 80 LF=57nm 70 W=19.5nm t p reduction (%) 60 V DD =0.7V 50 40 30 0.5fF 1fF 20 2fF 4fF 10 High I eff Increase 6fF vs C eq increase 0 2 3 4 5 6 7 8 9 10 11 Number of stacked GAA Saturation of t p reduction when the number of stacked nanowires increase (I eff increase from N to N+1 is close to C eq increase). 18.

Electron mobility in NW/NS FF mobility In GAA NanoSheet, µ electron is increased due to high mobility in the (100) plan. 19.

Hole mobility in NW/NS FF mobility [110] FinFET Horizontal GAA NS for n-FETs and vertical GAA NS for p-FETs turn out to be the most effective solutions to promote electron and hole transport, respectively. 20.

Outline • Performance/Design consideration • Device Fabrication – Inner spacer – SiGe S/D • Strain Characterization – Precession Electron Diffraction • Perspectives • Summary and Conclusion 21.

Devices Fabrication S/D x N -(SiGe/Si) EPI Horizontal Wires 1. EPI Growth Growth RMG Process (Si 0.7 Ge 0.3 /Si) Spacer 1 2. 300mm (100) SOI substrates Fin Patterning Deposition/Etch TEOS/Poly-Si (Si/SiGe) multilayer: ILD and CMP Dummy Gate Option1: Dummy Gate CMP Poly-Si ( Si /SiGe/ Si ) ≡ removal ( 12nm /12nm/ 12nm ) Dummy Gate Release of Option2: 4. Patterning stacked-NW ( Si /SiGe/ Si /SiGe/ Si ) ≡ Spacer 0 RMG module 5. ( 7nm /8nm/ 7nm /8m/ 7nm ) Deposition/Etch HfO 2 /TiN/W Inner Spacer 3. Contact Deposition/Etch Grey steps are not different BEOL modules that FinFET process-Flow 22.

Devices Fabrication Vertically stacked wires FETs Process-Flow Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Inner spacer formation Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contact/BEOL 23.

Devices Fabrication Vertically stacked wires FETs Process-Flow Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Inner spacer formation Source/Drain Epitaxy ILD & CMP S. Barraud & al. (IEDM 2016) Dummy Gate Removal Individual and dense arrays of Formation of Suspended NW fins were patterned to fabricate (release of NW) stacked wires FETs. 40 nm Fin Gate Stack Formation pitch / 60 nm height / 20 nm Contac/BEOL width 24.