Overview of Countermeasures against Implementation Attacks Marcel - PowerPoint PPT Presentation

Overview of Countermeasures against Implementation Attacks Marcel Medwed UCL Crypto Group Marcel.medwed@uclouvain.be Design and Security of Cryptographic Algorithms and Devices 1 Albena, May 2011

Outline 1. Motivation & general mechanisms 2. Side-channel countermeasures 3. Fault countermeasures 4. Conclusions Design and Security of Cryptographic Algorithms and Devices 2 Albena, May 2011

Motivation • Sensitive applications require certification – Pay TV, Banking,... – Standard portfolio of attacks • SCA • Fault analysis, probing • … • Cost security tradeoff Design and Security of Cryptographic Algorithms and Devices 3 Albena, May 2011

General Mechanisms Constant Detection Instantaneous Timing Leakage Limit measurements m 1 Faults m 2 c = E k (m) ... Probing ... m n Low SNR Independence Shielding Design and Security of Cryptographic Algorithms and Devices 4 Albena, May 2011

Side-Channel Countermeasures 1. Data independent timing 2. Hiding 3. Masking 4. Regular key updates Design and Security of Cryptographic Algorithms and Devices 5 Albena, May 2011

Data Independent Timing • Data dependent [ [ branches – Reduction, Compiler  Use regular algorithms  Use assembly code • Architectural features – e.g. ARM7 multiplier • time(0xFFFF*Op2) > time(0xFF*Op2) Design and Security of Cryptographic Algorithms and Devices 6 Albena, May 2011

Instantaneous Leakage • Leakage trace – Vector of t leakage samples • Sensitive variable v – Depends on key and input  • Observe noisy function of v – For some i, – E.g. L = Hamming weight Design and Security of Cryptographic Algorithms and Devices 7 Albena, May 2011

Hiding • In each clock cycle, consume either – (close to) random power  increase n  L(v) ~ const. – (close to) constant power • Hiding only decreases the SNR • Hiding dimensions – Time – Amplitude Design and Security of Cryptographic Algorithms and Devices 8 Albena, May 2011

Hiding in Software I • Time – Insertion of dummy operations – Shuffling time S 1 S 3 S 3 D S 2 S 3 S 4 S 4 S 1 D S 2 S 4 S 1 D D S 2 observations S 1 S 3 D S 2 S 3 S 4 D D S 2 S 4 S 4 D S 3 D S 1 D D S 2 D S 4 S 1 S 2 S 3 S 4 S 3 D S 4 S 1 D D S 2 D S 1 S 2 S 3 S 4 Design and Security of Cryptographic Algorithms and Devices 9 Albena, May 2011

Hiding in Software II – Effect of time randomization with n positions • Sample from with probability 1/n – Integration over all n positions • Noise increases linearly • Correlation ~ n -1/2 Design and Security of Cryptographic Algorithms and Devices 10 Albena, May 2011

Hiding in Software III • Amplitude – Peripheral activity • ADCs • Co-processors – Memory addresses • of dummy registers • of key dependent registers – Random precharge of bus • • Pure HD leakage? Design and Security of Cryptographic Algorithms and Devices 11 Albena, May 2011

Hiding in Hardware I • Time – Dummy instructions – Shuffling – Random jitters – Change clock frequency – Multiple clock domains Design and Security of Cryptographic Algorithms and Devices 12 Albena, May 2011

Hiding in Hardware II • Amplitude – Filters • Switching capacitors • Constant drain circuits – Noise generation engines – Parallelization – Pipelining / Unrolling – Dynamic reconfiguration (FPGAs) Design and Security of Cryptographic Algorithms and Devices 13 Albena, May 2011

Hiding at Cell Level • Dual-rail precharge logic styles Trans. l 0  0 0 a Single 0  1 1 q Rail b 1  0 1 1  1 0 Trans. l 10  00 1 a Dual ¬a q 01  00 1 b ¬q Rail 00  10 ¬b 1 00  01 1 Design and Security of Cryptographic Algorithms and Devices 14 Albena, May 2011

Conclusions for Hiding • Decrease the SNR – Increase noise – Decrease signal • Only minor changes to the algorithms • Check local SNRs • Noise is essential for masking! Design and Security of Cryptographic Algorithms and Devices 15 Albena, May 2011

Masking • Randomized redundant representation – • n th -order masking – All n-1 intermediate variables are independent of v – Adversary needs to • identify n leakage samples • and combine their information • Challenge – Usually achieving is not straightforward Design and Security of Cryptographic Algorithms and Devices 16 Albena, May 2011

Masking Few Bits I • Assume little structure (e.g. block cipher) – Boolean masking • • Alternatively – Multiplicative masking (zero-value problem) • – Affine Masking • Design and Security of Cryptographic Algorithms and Devices 17 Albena, May 2011

Masking Few Bits II • Marginal PDFs are independent  joint PDF W H (v)=0 W H (v) = 4 W H (v 2 ) W H (v 2 ) W H (v 1 ) W H (v 1 ) • Effect – k shares, sufficient noise – Number of traces relates to – Combination results in additional loss Design and Security of Cryptographic Algorithms and Devices 18 Albena, May 2011

Masking Few Bits III Combined Only masking Only shuffling Design and Security of Cryptographic Algorithms and Devices 19 Albena, May 2011

Masking in Software I • First-order masking  Lookup tables • Higher order masking – Secure table computation for 2 nd order masking – Test all subsets! • Check Hamming distance – Buses, registers,... Design and Security of Cryptographic Algorithms and Devices 20 Albena, May 2011

Masking in Software II • Rivain and Prouff – CHES10 – Provable secure masking for AES with arbitrary order – Based on Private Circuits • Cycle counts for a masked AES – Pay for security directly Masking order AES cycles in execution time w/o masking 2 000 1 10 000 2 271 000 3 470 000 Design and Security of Cryptographic Algorithms and Devices 21 Albena, May 2011

Masking in Hardware I v m S(v) m‘ Masked S-box m m‘ • Unclear what synthesizer does – Unintentional unmasking – Unintentional combination function • Data dependent glitches Design and Security of Cryptographic Algorithms and Devices 22 Albena, May 2011

Masking in Hardware II • Nikova et al. – Threshold implementation – Independent processing of subset of shares f 1 f 4 v 1 y 1 z 1 f 2 f 5 v 2 y 2 z 2 f 3 f 6 v 3 y 3 z 3 • If shares processed in parallel – Univariate leakage – But still higher order attack Design and Security of Cryptographic Algorithms and Devices 23 Albena, May 2011

Masked Logic Styles • Remove requirement for balanced routing – Average power consumption is constant (in theory) – E.g. MDPL NAND gate a m b m m ¬a m ¬b m ¬m q ¬q a m 0 0 0 1 1 1 1 0 SR b m q MAJ 0 1 0 1 0 1 1 0 m 1 0 0 0 1 1 1 0 1 1 0 0 0 1 0 1 ¬a m SR 0 0 1 1 1 0 1 0 ¬b m ¬q MAJ ¬m 0 1 1 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 1 Design and Security of Cryptographic Algorithms and Devices 24 Albena, May 2011

Exploiting Algebraic Structures • Scalar blinding • Message blinding • Embeddings Design and Security of Cryptographic Algorithms and Devices 25 Albena, May 2011

Using Inherent Redundancy • ECC point projection – Originally to avoid inversions – Free randomization Design and Security of Cryptographic Algorithms and Devices 26 Albena, May 2011

Conclusions for Masking • Take care of – Unintentional unmasking – Glitches – Lower order leakages • For small mask widths – PDFs can be estimated – But exponential increase in data complexity • For large mask widths (PKC) – Inexpensive and very effective Design and Security of Cryptographic Algorithms and Devices 27 Albena, May 2011

Key / Message Transformations • Sequential key update – E.g. with hash function • Indexed key update – Use invertible function • Parallel key update – Easy to protect key update function • Leakage resilient cryptography • Message transformation – Also apply to ciphertext Design and Security of Cryptographic Algorithms and Devices 28 Albena, May 2011

Evaluating Countermeasures • Correlation attacks might overestimate the security • Compute mutual information between leakage and sensitive variable • Attacks might become too sophisticated – lower bound moves far away from real security Design and Security of Cryptographic Algorithms and Devices 29 Albena, May 2011

Invasive-Attack Countermeasures • Fault injection prevention • Error detection C = f(A,B) D = f(A,B) ADD If (C != D) then XOR AND errorHandling(); CMP EndIf; www.coders4fun.com Design and Security of Cryptographic Algorithms and Devices 30 Albena, May 2011

Protecting All Points-of-Attack • Crypto – Data integrity • OS level – Self-check – Redundant state machines • Hardware level – Prevent physical access – Increase cost for physical access – Filter fault sources Design and Security of Cryptographic Algorithms and Devices 31 Albena, May 2011

Active-Attack Prevention • Shields • Sensors (e.g. light) • Filter power line • On-chip generation of clock signal • Limit number of operations • Burry sensitive parts Design and Security of Cryptographic Algorithms and Devices 32 Albena, May 2011