Overlay Metal/ Inter-dielectric layers/BCB/Cu Bump Workshop
Contributors � Contributions – Jerry Beene Sr. Photolithography Engineer – Roberta Hawkins Sr. Photolithography Engineer – Amy Zhou Sr. Photolithography Engineer – HT. Chen Sr. EBEAM Engineer – Martin Ivie Sr. Photolithography Engineer – Harold Isom Engineering Manager Confidential & Proprietary 2
Agenda � Agenda – Overlay Metals and Interconnects • Process Flow • MET0- – Evaporation and Liftoff – PVD Sputtering and Electroplating • NIT1-Interlayer Dielectric (ILD) – PECVD • MET1-MIM CAP – Etching � Dry � Wet • NIT2- CAP – PECVD • MET2-Air Bridge • Final Over-Coat – BCB – Copper Bump 3
Overlay Metal-Interconnects and Dielectrics � Overlay metals may be used to increase metal conductivity or to form other features such as transmission lines, inductors and bottom capacitor plates. Dielectric films may be applied for encapsulation or capacitor formation. A second or even third metallization can be used to form other connections. – Requirements • High electrical conductivity, good adhesion, effectiveness as a diffusion barrier, effectiveness as an etch stop. • High electrical conductivity can be met with four metals, gold, aluminum, silver and copper. � Dielectric films are used for encapsulation, for capacitor dielectrics and crossover insulators . – Requirements • There are generally just a couple of dielectrics used in GaAs Processing: Si3N4, and SiO2 and sometimes Ta02. • Si02 have a lower dielectric constant and are good cross-over, Si3N4 because of the higher dielectric constant are better suited for capacitors. Williams, Modern GaAs Processing Methods Confidential & Proprietary 4
Process Flow * Ohmic/Alloy Nitride 1 DC Probe * Isolation Cap Top Plate Wafer Thinning Wide Recess Nitride 2 Via Etch Gate Pattern Metal 1 Backside Metal Gate Fabrication Air Bridge Post Backside Plate * Nitride 0 Metal 2 RF Probe * * TaN Resistors Protective Overcoat Chip Separation * Metal 0 Saw Street Etch Final Visual * Optional Steps 5
MET0 (First layer Metal) 1st-Metal (MET0) Provides metal interconnect; overlay ohmic metal, Sputter TiWN /Ti Barrier � underlay plating (increases sheet conductivity). Sputter Ti//Pt/Au/Ti Seed layer. Used to contact TaN resistors. Can also be used � Coat/Align/Develop to Pattern 1st-Metal as the bottom plate in the capacitor. � First Layer metals can use a variety of deposition ADI Inspection � methods: Sputtering (PVD), Evaporation, PECVD ASH Descum to prepare for Plate � and electroplating. Gold-Plate, Resist-Strip, Seed-Deplate and Clean � (This can also be a evaporated metal) � ACI Inspection � Measure Metal CD’s � Barrier/Seed Etch (if not evaporated) TiWN/Ti Barrier strip in LAM590 � AEI Inspection � Resist Strip � Deveil to remove post-etch Polymers � Spin/Rinse/Dry � ACI Inspection � Confidential & Proprietary 6
Methods for Deposition � Different Methods – Growth • Thermal Oxidation (SiO 2 ), Titanium Nitride – Spin on Films • Spin on Dopants (SOD), Spin on Glass (SOG) – Deposition • Chemical Vapor Deposition (CVD) – APCVD (atmospheric pressure) – LPCVD (low pressure) – PECVD (plasma enhanced) – Epitaxial Growth (single-crystal films) • Physical Vapor Deposition (PVD) – Sputter – Evaporation • Electroplating Confidential & Proprietary 7
PVD-Evaporation � Physical Vapor Deposition (PVD) – Evaporation: – Vaporize a metal using thermal energy @ low pressure � An Evaporation system includes the following: – High vacuum chamber and high vacuum components – Evaporation source: Filament, Electron beam, or Flash hot plate � Evaporation is Inferior to Sputtering: – Difficult to do alloys – Step coverage – Adhesion Confidential & Proprietary 8
Evaporation /Lift-Off � Evaporated metal is deposited on top of the resist rather than using the resist as an etch mask. � Requires an overhang to form a break between the metal on the resist and substrate. � Called lift-off because if the wafer is soaked in solvent, the resist will dissolve and metal is left free to lift-off. 9
Components of a Evaporator Confidential & Proprietary 10
Evaporation and Liftoff Source : Temescal 11 Confidential & Proprietary
Common Lift-Off Methods Method Advantages Disadvantages Positive or Negative Tone Bi-layer High resolution Expensive material. 1 st layer planarizes. Requires non standard EBR chemistry. Requires high temp bake. AZ-5214E-IR Single coat Temperature sensitive. Requires UV flood expose. Etch assisted High resolution Unusual for substrate to allow etching Positive Only Developer Soaks Lip at top allows thick lift-offs Does not work for all resists. Negative Only AZ NLOF High resolution Difficult to strip Single coat Ammonia bake Requires specialized oven for ammonia. 12
Simple Bi-layer Coat PMGI and hot plate bake Coat resist and hot plate bake Stepper expose Develop 13
Bi-layer for Undercut Control Coat PMGI and hot plate bake Coat resist and hot plate bake Stepper expose Develop resist DUV expose Develop PMGI 14
AZ5214 Partial Image Reversal (Positive) Coat and hot plate bake Short flood expose and bake To crosslink exposed resist Stepper expose Develop 15
AZ5214E Image Reversal (Negative) Coat and hot plate bake Stepper expose Cross linking bake UV Flood Expose Develop 16
Etch Assisted lift-off Coat and hot plate bake Stepper expose Develop Etch 17
Developer Soak Coat resist and hot plate bake TMAH Soak Stepper expose Develop 18
nLOF Lift-off Coat and hot plate bake Stepper expose Cross linking bake Develop 19
Ammonia Bake Coat and hot plate bake Stepper expose Ammonia bake UV Flood Expose Develop 20
Lift-Off Challenges � The processes tend to be complicated. � Small resist lines can suffer adhesion loss due to the undercut. � The degree of undercut can be difficult to monitor without cross section. � Evaporated metal will be shifted within the resist opening as distance is increased from the wafer center. 21
Sputtering � Process Concerns with Sputtering: – Hillock Growth: Excess heat generated by the plasma can cause hillock growth, grains which relieve the stress in the film by growing upward. – Poor Step Coverage due to physical nature of the process. – Contamination Metal Step Coverage 1000A Ti Deposited in Back Deposition 23 Via (pre-plate) Confidential & Proprietary 22
PVD and Sputtering � Physical Vapor Deposition (PVD) - Sputtering: – Use plasma energy to blast small fragments from a target. – Purely physical process, no chemical reaction occurs. – Reverse of physical etching (sputter etch), used at the beginning of the sputter process to remove native oxides. � Where is Sputtering Used? – Because it is a physical process, almost any material can be sputtered (CVD is limited to materials that can be chemically created). – In III-V processing, sputtering is most often used to deposit seed metals before electroplating Interconnect or create barrier layers: Confidential & Proprietary 23
Electroplating � There are two main gold plating baths in industry today, cyanide based and non- cyanide baths containing either sulfite or thiosulfate as the primary electrolyte. The cyanide bath is by far the dominant of the two. � Gold (Au) is ionized in the solution at the +1 oxidation state. The gold is plated using the wafer as a cathode attracting the positively charged gold ions to the surface and reducing them to Au(s). � Operation of the gold electroplating bath involves constant monitoring of key process parameters, which include gold reflectivity, film stress, and film thickness . Advances in Gold Metallization at Motorola's Compound Semiconductor Fab (CS1) Chad M. Becker, William Rummel*, Dr. Paul Ocansey Confidential & Proprietary 24
Plating Issues • Problem Description – The haze comes from two sources: Incomplete deplate leaving behind Au islands and un-removed TiW from the barrier wet etch – Au Islands create leakage paths and have created scrapped material. This is the same failure as EMODE which resulted in the loss of 180 wfrs. – TiW residue is not known to cause yield loss, but cannot be distinguished between Au islands. Confidential & Proprietary 25
Cause and effect Diagrams for Plating Issues Source: Paul Ocansey Confidential & Proprietary 26
NIT1 (First Interlayer Dielectric, ILD) � Interlayer dielectrics (ILD) can be used for a variety of applications such as encapsulation, insulating two metalization layers (MIMS). As well as capacitors � Key characteristics : Dielectric constant is dependent on deposition method and parameters. If a dielectric film is too thin, there will be a larger amount of pinholes if it is too thick then the parasitic capacitance will increase. � The formation of the film can affect saturation current, breakdown voltage as well as other parameters. Confidential & Proprietary 27
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