Overflow in addition and subtraction can happen if?? ta7 What - PDF document

Overflows הנבמ � Overflow in addition and subtraction can םיבשחמ happen if?? ta7 � What can we do if there is an overflow?? Spring 2006 � MIPS support two kinds of arithmetic operations in order to support the two choices � Add (add) , add immediate (addi), subtract (sub) Amar Lior cause exception � Add unsigned (addu), add immediate unsigned (addiu), subtract unsigned (subu) do not cause exception � C ignore exception so the compiler must use the Adapted from Computer Organization&Design, H/S interface, Patterson Hennessy@UCB,3 rd edition operations which does not cause exception 1 4 Signed versus unsigned comparison Checking for overflow � IF we still want to detect an overflow we can do: � Supposed register $s0 has the binary number addu $t0, $t1, $t2 # $t0=sum but don’t trap � 1111 1111 1111 1111 1111 1111 1111 1111 xor $t3, $t1, $t2 # Check if sign differ � And $s1 has: slt $t3, $t3, $zero # $t3=1 if sign differ bne $t3, $zero, No_Overflow � 0000 0000 0000 0000 0000 0000 0000 0000 xor $t3, $t0, $t1 #checking sign of sum � slt $t0, $s0, $s1 slt $t3, $t3, $zero # $t3=1 if sum sign different � sltu $t0, $s0, $s1 bne $t3, $zero, Overflow 2 5 Right shift is the same as integer division in Bounds Check Shortcut power of 2 � How can we reduce the cost of checking if � Suppose we want to divide -5 by 4 � 0 <= X < Y � The quotient should be -1 � The key is that negative numbers in two’s complement looks like large numbers in unsigned � The two’s complement representation of -5 notation � 1111 1111 1111 1111 1111 1111 1111 1011 � The most significant bit is a sign bit in tow’s complement � If we shift right by 2 bits we will get � And it is a large part of the number in the unsigned � 0011 1111 1111 1111 1111 1111 1111 1110 notation � The value is 1,073,741,822 instead of -1 � The code: sltu $t0, $a1, $t2 � The solution?? beq $t0, $zero, IndexOutOfBounds 3 6 1

ABS ?? Floating Numbers in MIPS � addu $s1, $zero, $s2 � The MIPS has a floating point coprocessor � bgez $s2, 8 � It operate on single precision (32-bit) � sub $s1, $s0, $s2 � And also on double precision (64-bit) � Has its own registers $f0-$f31 � Because the registers are only 32-bit wide � Two of them are required to hold doubles � To simplify, floating points operations only use even-numbered registers � Has 8 condition codes flags (cc), 0-7 7 10 ABS?? Floating-point data movement (MIPS) � Load to coprocessor 1 (base address is an integer register) � lwc1 $f1, 100($s2) � l.s and l.d can also be used � Store from coprocessor 1 � swc1 $f1, 100($s2) � s.s and s.d can also be used � Move from coprocessor 1 � mfc1 $f1, $s2 � Move to coprocessor 1 � mtc1 $s2, $f1 � Move inside coprocessor 1 � move.s $f2, $f4 move.d $f2, $f4 8 11 Floating point addition is NOT associative Floating-Point Instructions in MIPS 1 . 5 * 10 38 , 1 . 5 * 10 38 , 1 . 0 x = − y = z = ten ten � MIPS supports the IEEE 754 single precision and � Suppose double precision with the following instructions � Then: � Addition single (add.s) double (add.d) � Subtraction single (sub.s) double (sub.d) 38 38 + ( + ) = − 1 . 5 * 10 + ( 1 . 5 * 10 + 1 . 0 ) = x y z ten ten � Multiplication single (mul.s) double (mul.d) 1 . 5 * 10 38 ( 1 . 5 * 10 38 ) 0 . 0 − + = � Division single (div.s) double (div.d) ten ten � Comparison single (c.x.s) double (c.x.d) ( ) ( 1 . 5 * 10 38 1 . 5 * 10 38 ) 1 . 0 x + y + z = − + + = � Where x may be equal (eq), not equal (neq), less than ten ten (lt), less than or equal (le), grater than (gt), or grater 0 . 0 + 1 . 0 = 1 . 0 than or equal (ge) � Branch true (bc1t) false (bc1f) 9 12 2

Floating point directives The Floating-point bug � The Pentium FDIV bug is the most famous (or � .float f1,f2,…,fn infamous) of the Intel microprocessor bugs. � .double d1,d2,…,dn � It was caused by an error in a lookup table that was a part of Intel's SRT algorithm that was to be faster and more accurate. � With a goal to boost the execution of floating-point scalar code by 3 times and vector code by 5 times, compared to the 486DX chip � Intel decided to use the SRT algorithm that can generate two quotient bits per clock cycle, while the traditional 486 shift-and-subtract algorithm was generating only one quotient bit per cycle. 13 16 Example The Floating-point bug # Converting from # Fahrenheit to calicos float f2c (float fahr) { return ((5.0/9.0) * (fahr – 32.0)); � This SRT algorithm uses a lookup table to calculate # Argument in $f0 } the intermidiate quotients necessary for floating- # Result in $f12 point division. � Intel's lookup table consists of 1066 table entries, f2c: of which, due to a programming error, five were l.s $f16, CONST5_F not downloaded into the programmable logic array l.s $f18, CONST9_F (PLA). div.s $f16, $f16, $f18 � When any of these five cells is accessed by the l.s $f18, CONST32_F floating point unit (FPU), it (the FPU) fetches zero sub.s $f18, $f0, $f18 instead of +2, which was supposed to be contained mul.s $f12, $f16, $f18 in the "missing" cells. jr $ra � This throws off the calculation and results in a less precise number than the correct answer 14 17 Parallel operations � MIPS-32 added “paired single” version of all � At its worst, this error can occur as high as floating point instructions the fourth significant digit of a decimal � A single instruction results in two parallel number floating point operations on two 32-bit � but the possibilities of this happening are 1 operands in 360 billion. � Example add.ps F0, F2, F4 is equivalent to � It is most common that the error appears in � add.s F0, F2, F4 the 9th or 10th decimal digit � add.s F1, F3, F5 � which yields a chance of this happening of 1 � The intel SSE2 (Streaming SIMD Extension in 9 billion. 2) is similar 15 18 3

� July 1994: Intel discovers the bug. The actual cost to fix was several hundred $$ � Intel decided not to fix but to wait until a new version of the processor comes out in January 1995 � September 1994: A math professor at Lynchburg College in Virginia, Thomas Nicely discovers the bug � November 7, 1994 Electronic Engineering Times puts the story in his front page … 19 � November 22, 1994: Intel issue a press release calling the bug a glitch … � December 5, 1994: Intel claims the flow happens once in 27,000 years for the typical spreadsheet user � December 12, 1994: IBM Research Division disputes Intel’s calculation claiming an error as often as once every 24 days � IBM stops shipment of all IBM personal computers based on this chip � December 21, 1994: Intel decide to replace any faulty chip free of charge asking no questions …. � Analysts estimate this recall cost Intel $500 million 20 4