SMT Attack : Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks Conference on Cryptographic Hardware and Embedded Systems 2019 ( CHES 2019 ) Kimia Zamiri Azar , Hadi Mardani Kamali, Houman Homayoun, and Avesta Sasan Department of Electrical and Computer Engineering George Mason University, USA.
Outline Intro to Hardware Security Intro to Logic Locking SAT Attack and its Limitations SMT attack SMT reduced to SAT Attack Eager SMT Attack Lazy SMT Attack Accelerated Lazy SMT Attack Experimental Results Conclusion 2
Design Flow High Cost of Manufacturing in ASIC Design has pushed most of needed fabrication offshore Some Fabs are untrusted Security threats for untrusted supply chain Trojan Insertion Overproduction Intellectual Property (IP) Theft Counterfeiting Reverse Engineering, etc. In-house SoC Design Flow System Design Design Teams IP Vendor 1 Physical Synthesis RTL Verification PCB Assembly Logic Synthesis Gate-Level Verification Integration Package & Assembly Design Layout (GDSII) Layout Netlist Netlist System RTL Wafer Test Recycle/Repackage for Outdated IP Vendor 2 Integration Team Fabrication Design Synthesis & Verification Testing Packing System Integration 3
Logic Locking Logic Locking : Adding Ambiguity to the Design Inserting Key Programmable Gates ( KPGs ) No Information on Key at Untrusted Entities x 1 x 2 Y = f(x 1 , x 2 , …, x n ) x 3 Original Netlist Circuit x 4 x n Logic Locking EPIC (2008) x 1 x 2 Random Y n = f(x 1 , x 2 , …, x n , k 1 , k 2 ) Insertion x 3 k 1 Policy x 4 (RLL) k 2 x n 4
SAT Attack: a Turning Point in Logic Locking SAT Attack Recipe: Reverse-engineered netlist (CL) 1. k 0 A functionally activated chip (CO) I 0 2. kg 0 g 2 I 1 O 0 g 0 g 5 I 2 g 3 O 1 I 3 g 6 g 1 I 4 g 4 kg 1 I 5 k 1 SAT attack broke all logic obfuscation scheme prior to its debut! Random insertion (RLL) Fault-analysis (FLL) Interference-based logic locking (SLL) 5
SAT Attack SAT Attack Key- SAT Circuit Obfuscated Key-Differentiating DI Validation SCK Validation Programmable (SATC) Circuit Circuit (KDC) Circuit (DIVC) Circuit (SCKVC) Circuit (KPC) (1) X DI K 1 (2) . C Locked (X, Y) K 1 C(X,K,Y) C(X,K 1 ,Y 1 ) ꓥ C(X,K 2 ,Y 2 ) ꓥ (Y 1 !=Y 2 ) X DI . DIVC SCKVC KPC K1 (1) ( d ) X DI KPG X DI KPG KPC Y1 X DI ORACLE eval DIVC X K 1 K (2) KPG . X DI K 2 KDC . Y . Y X KPG K 2 KPC Y2 KPC X X K2 K 2 Y 2 KPG DIVC LC ( d ) X DI Set of Correct Keys (SCK) Set of Invalid Keys (SIK) Clause added Clause added Clause added Clause added Breaks within few minutes (few iterations)! 6
Limitation of SAT Attack SAT-Resilient Logic Obfuscation Solutions SAT-Resilient Locking Schemes Logical Locking DLL 2017 No Defense Cyclic Locking 2016 RLL 2008 Scheme LUT-Lock 2018 Against All FLL 2015 SARLock 2016 SRCLock 2018 Reconfig. Threats Anti-SAT 2016 SFLL 2017 Barrier 2010 SLL 2012 SAT Before 2008 2008 – 2010 2010 – 2015 2016 2017 2018 IP Piracy Removal 2016 Sensitization & CycSAT 2017 Overproduction SPS 2016 Justification 2012 Counterfeiting SAT SMT AppSAT 2017 Reverse Attack Attack Double-DIP 2017 2015 Engineering Bypass 2017 7
Limitation of SAT Attack A SAT Attack works if Logic obfuscation is of Boolean nature Model Translation Flow: Boolean logic Conjunctive Normal Form ( CNF ) CNF Satisfiability assignment problem SAT-Resilient Locking Schemes Logical Locking Defense solutions to trap the SAT solver? DLL 2017 Cyclic Locking 2016 Use non-logical properties for locking LUT-Lock 2018 SARLock 2016 SRCLock 2018 Can not be modeled if could Anti-SAT 2016 SFLL 2017 not be translated to CNF SAT 2016 2017 2018 Removal 2016 CycSAT 2017 SPS 2016 SAT SMT AppSAT 2017 Attack Attack Double-DIP 2017 2015 Bypass 2017 8
Behavioral logical obfuscation Delay and Logic Locking (DLL) Obfuscation control the setup and hold Incorrect key Setup and Hold time violation Timing is not translatable to CNF SAT solver remains oblivious to the keys used for timing obfuscation Tunable Delay Buffer (TDB) k 1 k 1 Tunable Delay y y k 2 x key-gate x k 2 k 2 (TDK) C 9
Solution Satisfiability Modulo Theory (SMT) Attack 10
SMT Solver A SMT is used to solve a decision problem Close integration of a SAT solver with Theory solver Uses first-order theories Equality Reasoning Arithmetic Graph-based deduction Modern SMT solvers provide the capability Combining theory solvers Can support more powerful languages as its input 11
Approaches to SMT Solver Two approaches for solving an SMT problem Eager approach Lazy approach µ µ Theory µ* Theory SAT Solver SAT Solver SAT/UNSAT SAT/UNSAT Lazy approach Eager approach 12
SMT Eager Approach Eager approach Translating the problem into a Boolean SAT instances The existing Boolean SAT solvers are used as is The SMT solver has to work a lot harder e.g. for checking the equivalence of two 32-bit values By deploying a theory solver µ this could be achieved in no time Theory µ* SAT Solver SAT/UNSAT 13
SMT Lazy Approach Lazy approach Integrates the Boolean satisfiability solvers and theory solvers Capabilities of the Theory solvers: Theory propagation for checking possible conflicts on partial assignments Clause learning to speed-up pruning the decision tree. µ Theory SAT Solver SAT/UNSAT 14
SMT Attack ... Bit-vectors Arrays Equality Graph SMT solver Graph Quantifier-free Update Update extraction SMT solver T LC SMT LC Theory-2 extraction ... Graph SAT solver solver Theory-n Translation extraction Theory solvers module Update SAT CC + LLK Obfuscated netlist Circuit extraction SAT/UNSAT 15
SMT Attack Step 1 Obfuscated cells equivalent Key Programmable Gates ( KPG ) A KPG performs the same function as the obfuscated cell allows building a key controlled representation ... Bit-vectors Arrays Equality Graph SMT solver Graph Quantifier-free Key Gate Key Gate Translated Gate Translated Gate Update Update extraction SMT solver T LC SMT LC i 0 4. XOR Gate Theory-2 1. Tunable Delay Gate extraction ... k 1 k 1 Graph i 0 SAT k 0 TDK i 1 i 1 solver solver Theory-n k 1 Translation k 0 k 1 extraction Theory solvers module Update k 0 2. Look-Up-Table 5. MUX SAT CC + LLK k 1 i 1 Obfuscated netlist Circuit i 1 k 2 LUTn i 2 ... extraction i 2 n k 2 -1 k 1 i 0 i 1 i 2 i n-1 ... k 1 SAT/UNSAT i 0 i 1 i 2 i n-1 k 1 i 1 3. Camouflaged Gate 6. XNOR Gate k 1 i 2 k 1 i 1 i 1 i 1 AND/XOR i 2 16
SMT Attack Step 2 Before invoking a theory solver Input model model which is understood by that theory solver Different translation step for each theory solver ... Bit-vectors Arrays Equality Graph SMT solver Graph Quantifier-free Update Update extraction SMT solver T LC SMT LC Theory-2 extraction ... Graph SAT solver solver Theory-n Translation extraction Theory solvers module Update SAT CC + LLK Obfuscated netlist Circuit extraction SAT/UNSAT 17
SMT Attack Invoking the SMT solver returns A satisfiable assignment list of learned theory conflict clauses ... Bit-vectors Arrays Equality Graph SMT solver Graph Quantifier-free Update Update extraction SMT solver Theory-2 T LC SMT LC extraction ... Graph SAT solver solver Theory-n Translation extraction Theory solvers module Update SAT CC + LLK Obfuscated netlist Circuit extraction SAT/UNSAT 18
Attack Modes Mode 1 : SMT reduced to SAT Attack To show SMT is a superset of SAT Mode 2 : Eager SMT Attack To show the Strength of SMT Theory solver(s) and SAT solver are Serialized! Mode 3 : Lazy SMT Attack To show the Strength of SMT Theory solver(s) and SAT solver are Parallelized! Mode 4 : Accelerated Lazy SMT Attack (AccSMT) To show more efficiency Uses BitVector Theory Solver 19
Attack Modes Mode 1 : SMT reduced to SAT Attack To show SMT is a superset of SAT Mode 2 : Eager SMT Attack To show the Strength of SMT Theory solver(s) and SAT solver are Serialized! Mode 3 : Lazy SMT Attack To show the Strength of SMT Theory solver(s) and SAT solver are Parallelized! Mode 4 : Accelerated Lazy SMT Attack (AccSMT) To show more efficiency Uses BitVector Theory Solver 20
Mode 1: SMT reduced to SAT Attack SMT solver is a superset of SAT solver Any attack formulated for SAT can be formulated using SMT one-to-one translation of the original SAT attack 21
Mode 1: SMT reduced to SAT Attack The recently found Conflict Clauses (CC) are added to the set of previously found Learned Clauses (LC). Note that this step is done implicitly if SMT is stateful . 22
Attack Modes Mode 1 : SMT reduced to SAT Attack To show SMT is a superset of SAT Mode 2 : Eager SMT Attack To show the Strength of SMT Theory solver(s) and SAT solver are Serialized! Mode 3 : Lazy SMT Attack To show the Strength of SMT Theory solver(s) and SAT solver are Parallelized! Mode 4 : Accelerated Lazy SMT Attack (AccSMT) To show more efficiency Uses BitVector Theory Solver 23
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