O N A C HIP S TACK WITH I NDUCTIVE C OUPLING T HROUGH C HIP I - PowerPoint PPT Presentation

1 1 3D L AYOUT OF S PIDERGON , F LATTENED B UTTERFLY AND D RAGONFLY O N A C HIP S TACK WITH I NDUCTIVE C OUPLING T HROUGH C HIP I NTERFACE Hiroshi Nakahara † , Ryota Yasudo † , Hiroki Matsutani † , Michihiro Koibuchi †† , Hideharu Amano † † Keio University, Japan †† National Institute of Technology, Japan

2 2 BACKGROUND AND MOTIVATION

3 3 Network-on-Chip • Network-on-Chip (NoC) is widely used. • The data are exchanged between routers as packets. • High degree of scalability compared with on-chip buses. Tile Router Chip is divided into tiles with a router

4 4 Topologies of NoCs • Most of NoCs use 2D mesh topologies. • Routers can be connected with short links. • High clock frequency However, the number of links between source and destination (hop count) becomes large. • Topologies with long links reduce hop count. • Spider ergon, F , Flatten ened ed B Butter erfly, D , Dragonfly , etc. However, long links limit clock frequency.

5 5 Example — Flattened Butterfly [1] loooooong link [1]. J. Kim, J. Balfour, and W.J. Dally, “Flattened butterfly topology for on-chip networks,” 40th Annual IEEE/ACM International Symposium on Microarchitecture, 2007. MICRO 2007., pp.172–182, Dec. 2007.

6 6 Our question Possible ?! 3D la D layout w with s h sma mall ll 2D la D layout w with s h sing ngle le la large c chi hip mult mu ltiple le c chi hips

7 7 Our goal • Propose 3D layout with multiple chips to reduce the maximum link length • In this paper, we study three existing topologies • Spidergon, Flattened butterfly, Dragonfly

8 8 3D CHIP STACKING TECHNOLOGY

9 9 3D stacking technology Wired Wireless (face-to-face) Two chips Flexibility Microbump Capacitive coupling Three chips or more Scalability Through silicon via Inductive coupling

� 10 10 CPU C U Core ThroughChip Interface (TCI) Network Int k Interface It consists of Da Data L Link nk Receiver coils (Rx) and Transmitter coils (Tx). Clo lock k Link nk Rx Rx Tx Tx Tx Tx Accele lerator C Core Host CPU Network k Interface Int Network k Interface Int TCI TCI I Rx Rx Tx Tx Tx Tx Tx Tx Rx Rx Accelerator 1 Rx Rx Tx Tx Tx Tx Tx Tx Rx Rx Accelerator 2

11 11 Most wires are used for only testing and debugging

12 12 TCI allows flexible structure TX TX Layer 3 CLK Layer 2 TX Layer 1 RX TX RX Layer 0 RX TX ⇔ Chips can horizontally be shifted Example 1. Multiple chips in one layer RX TX Layer 3 Layer 2 Layer 1 RX TX Layer 0 Example 2. Links connecting distant chips

13 13 PROPOSED METHOD: 3D LAYOUT USING TCI

・・・ ・・・ ・・・ ・・・ 14 14 Flattened butterfly topology [Kim et al., MICRO’08] • The topology depends on # of dimension . • The diameter is equal to # of dimension (quite low) We focus on this case. 1-dimension 2-dimension 3-dimension Flattened butterfly Flattened butterfly Flattened butterfly Low-diameter Scalable

15 15 If we use a single chip… (2D layout) • The maximum link length becomes large. … … … …

Each chip constitutes 2-dimension flattened butterfly. 16 16 Proposed method (3D layout) … … … … • Simply replace long links with vertical links. 2D layout Layer 3 Layer 2 Layer 1 Layer 0 # of routers must be n 3

17 17 Dragonfly topology [Kim et al., ISCA’08] • High performance network for off-chip interconnection. • Already used in supercomputers listed in TOP500. Routers in a group constitutes a clique. All the groups constitute a clique.

18 18 If we use a single chip… (2D layout) • Inter-group links becomes long. group Example: 4 routers in a group

19 19 Proposed method (3D layout) • All the inter-group links are replaced with vertical links. • The longest link is a inner-group link. • The maximum link length depends on the number of routers in a group. Layout on a chip (a group) Vertical links from Layer 0

20 20 Spidergon topology Circle + normal lines # of nodes must be even.

21 21 Spidergon can be represented as ladder-like structure Two cross links are needed ≡

22 22 If we use a single chip… (2D layout) folding ‘ladder’ Cross links become longer as # of nodes increase

23 23 Proposed method (3D layout) • Each chip has four nodes. H-1 CH-1,0 CH-2,0 CH-2,1 .... .... • Use multiple chips in one layer. 2 C2,0 C2,1 • so to speak, ‘ring-shaped ladder’ C1,0 C1,1 1 0 C0,0 Multiple chips in one layer. Cross links exist on a single chip! Layer 3 Layer 2 Layer 1 Layer 0 # of routers can increase by 8.

24 24 RESULTS

・ ・ ・ 25 25 The maximum link length (Flattened butterfly) √ O ( N ) √ 3 O ( N )

26 26 The maximum link length (Dragonfly) • In our 3D layout, the maximum link length depends on the number M of routers in a group. √ √ O ( M ) N − √ √ O ( M ) N − √ O ( M ) √ O ( M )

27 27 The maximum link length (Spidergon) √ O ( N ) O ( 1 )

28 28 CONCLUSION

29 29 Conclusion • 3D layout methods using TCI are proposed for the following three topologies with long links. • Flattened butterfly • Dragonfly • Spidergon • Our methods reduce the maximum link length. • In particular, 3D layout of Spidergon has the constant maximum length for any number of nodes.