NRAM D Defines a a New C Categor gory o of “Memory C Class S ss Storage” Bill Gervasi Principal Systems Architect 11 April 2019
2 NR NRAM Technol ology ogy Value Te Test Propos osition on Results ts Age genda Marke ket Product ct Positi tion De Design gns Future Roadmaps
3 When en w was the l last t time e you r read a about a a new ew v volati tile e memory? NRA RAM MR MRAM PCM CM 3DX DXP ReRAM Re The n e non-vola latile le me memory y revolu olution ion i is under w way
The Value Proposition for NVRAM is Obvious 4 NVDIMM Know DRAMs u used f for c caches es l lose e data on p power er f fail An en ener ergy s store i is need eeded t to save d data Yo Your Non on-vola latile ile m memory elim limin inates this is p problem Enemy my Batter eries es o or Super erCaps? NVMe Step on on g glas lass or or a a LEGO?
Checkpointing Eats Energy & Performance 5 No Non-Volatile M e Memory DRAM AM Run Run Run Chec eckpoint SSD/HDD Run Run Run Chec eckpoint SSD/HDD Run Run Run Chec eckpoint SSD/HDD
6 Imagi magine… A N A Non-Vola latile ile DD DDR Dr Drop op-In In …………….. …………….. Replacem emen ent… ……………..
7 …Using ng Carbon Nano notube ubes
8 Wi With… DRAM s spee eed Non on-vola latili ility Unlimited wr write en endurance Wide te e temper eratu ture e range Scalable b e bey eyond D DRAM Flexib ible f fabric ication ion & & applic icatio ion Low ow p pow ower Low c cost st
Carbon Nanotubes (CNT) 9 Nanotubes a are i in full p production t today Fundam amental al r resistan ance i is constan ant Leng ength a and nd d diameter er can b n be selec ected ed Mec echanically, t ther hermally, & elec ectrically s stable
CNT Nonvolatile Memory Cell 10 ELECTROD ODE ELECTROD ODE Van d n der W Waals e ener ergy b barrier er keep eps C CNTs s apa part or together er Data reten ention > >10 0 years ( (more l e like e >1000 y 000 years) s) Stocha hastic a array of hundr ndreds ds nano notub ubes p per e each c cell
CNT Mechanism Animation 11 TOP METAL + RESET: F ↑ Void stretches above BE SET: Void Shrinks F above BE + BOTTOM ELECTRODE
Resistance Measurements, 0 and 1 12 No c calibrati tion req equired a across the w e wafer MLC h has b bee een tes ested a as w wel ell
No Temperature Sensitivity in Timing 13 No c o chan ange f from om -55 55 ֯ C to to + +300 300 ֯ C 5 ns rea ead/write p per er c cel ell 13 cyc een in 10 13 No wr write en endurance l limits ts s seen ycles
Scalability 14 Key f factor i is the he num number o of CNT junc unctio ions ns pe per bi bit (>100 ne neede ded) Swi witching demonstrated f from 180n 180nm t to 15n 15nm Modeli ling s sho hows viabil bilit ity t to 1 1 nm nm l logic ic pr process
Flexible Fabrication & Application 15 Ei Eith ther… Or Bo Or Both th nR Crossp spoint 1T-1R m 1T matr trix 1T-1R m matr trix nR Crossp spoint 1T-1R m 1T matr trix 1T-1R m matr trix nR Crossp spoint nR Crossp spoint Function o of Desi sign E Efficien ency Cro rossover a aro round Hig igh M Mb or or low G Gb Logi gic/Memory p process Substra rate
Transistors in the Array 16 More like t tradit itio ional D l DRA RAM; be better f for s small ll arrays Plate Dra rain Dra rain Dra rain Wafer er / / C Circuits 1T-1R NRAM in Memory Process
Memory Crosspoint Structure 17 Cel ells c constructed ed from res esistive el elem ements between en l lines es Sel elf-selecting due due t to extremely ly low l leakage V1<0> V2<0> V1<1> V2<1> V1<2> V2<2> V1<3> V2<3> V1<4> V2<4> V1<5> V2<5> V1<6> V2<6> V1<7> V2<7> H1<0> 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 H2<0> 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 V1 V1 H1<1> H2 H2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 H2<1> 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 V2 H1<2> 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 H2<2> 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 H1 V1 H1<3> 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 H2<3>
Making a DRAM Replacement With CNT 18 X Y NRAM AM L LAYE YER Z Drivers rs Recei eiver ers Tune t e the e array s size e to the e size e of d drivers & & rec eceivers Chi hip-level t tim iming i is a function o of bit li line fli light tim imes Repl plicate t thi his “ “tile” as ne neede ded f for de device capa pacit ity Add I dd I/O dr drivers to emula ulate a any PH PHY ne neede ded 64 Kb tile X 256 K tiles = 16 Gb I/O PHY
Many I/O Types Possible 19 NR NRAM Core re eRAM AM Cust stom Technol ology ogy HBM BM GDDR DR HMC LPDDR DDR DDR DR4/ 4/DDR DDR5
DDR4 NRAM 20 A0:16 BG0:1 3DS DS stackabl ble BA0:1 DDR4 DDR 4 NR NRAM PAR 16 16 Gb p per d die C0:2 128 28 Gb per s stack ck CMD CK DQ0:3 LDQS DQ4:7 UDQS
DDR4 NRAM Overview 21 Carbon N n Nanotube ube A Arrays 72 bits Row Ro Colu olumn Bank Decode de Decode de Decode de SEC ECDED ED EC ECC Engi gine Address 64 bits FIFO FO FIFO FO Chip ID Die S e Selec ector x4/x /x8 Data Strobe Strobe Data
Latching Sense Amps & Persistence Control 22 CNT A Arra rray ACTI TIVATE TE Background und trans nsfers d data shadow b buffers fro rom a arra ray to allo llow c com ommits sense a nse amps to N o NV a V array Latchi hing S Sens nse A Amp Shadow B Buffer er READs Ds a and Vs DDR s DDR4, WRITEs f flow Slig lightly ly l longer t RCD CD , throug ugh s h sense a amps ps signif ific icantly s shor orter t AA AA t PERS RSIST = 4 46.25 n 25 ns ACT AC WRITE Benefi fit: F Fixed ed l laten tency to to External t AA DATA ATA t RCD CD AA Internal data p per ersistence CNT NT Loads LS Lo LSA Updates L LSA SA Shadow c copy fro rom C CNT with h ex ext data ta
Timing Similar to DDR4E, Faster than DDR5 23 Para rameter DDR DR4-2666 2666-D 3DS 3DS NRAM4 M4-2666 2666 DDR DR5-4400C 4400C tRC RC 47.00 47. 00 46.25 46. 25 50. 50.18 18 Activate t e to a activate tRC RCD RAS AS t to C CAS AS 15.0 15. 23.0 23. 18.18 18. 18 tAA Rea ead t to d o data 17. 17.14 14 13.5 13. 18. 18.18 18 tRP RP 15. 15.0 14. 14.25 25 18.18 18. 18 Precharg rge tRAS 32.0 32. 32. 32.0 32. 32.0 Activate t e to prechar arge tWR WR 15. 15.0 23. 23.0 45. 45.0 Write r recovery tFA FAW 21.0 21. 0 21.0 21. Fou our a activate w win indow l lim imit it tRFC FC 550 550 0 295 295 Refresh esh t time _L / _L / _S _S Bank g k grou oup t to b bank g k grou oup _S S Slower No pe pena nalty _S S Slower 3D 3DS Chip t to chip i in stack 2ck pe pena nalty No pe pena nalty 4ck pe pena nalty Latency: smaller is better
Bus Efficiency Comparison at Same Frequency 24 15-20% DDR4/DDR5 NRAM Base t throug ughp hput ut Elimination o of ref efresh sh Archi hitec ectural i impr provem ements improve ve data t throug ughput hput Elim limination of of tFA FAW restrictions 15% o 15 % or grea eater er at t the s he same clock f freque uenc ncy Elimina nation o n of bank g group p restrictions ns Elimination o of power er s states es Elim limination of of in inter-die d e delays Bandwidth: larger is better
DDR NRAM Scalability 512 Gb 512 Gb 25 7 nm l log ogic ic 8 8 layers C s CNT Add layers ~100 mm 2 256 Gb 256 Gb 7 nm l log ogic ic 4 layers C 4 s CNT 128 Gb 128 Gb 14 nm l log ogic ic 8 layers C 8 s CNT DDR DR5 New process Design gn Add layers Done 64 Gb 64 14 nm l 14 log ogic ic 4 4 layers rs C CNT DDR DR4 New process 16 Gb 16 28 28 nm l log ogic ic 4 layers 4 rs C CNT Add layers 16-di 16 die s e stacks 8 Gb 8 8-di die s e stacks 28 28 nm l log ogic ic 2 2 layers rs C CNT
Next Generation Main Memory Issues 26 A qui quick pe peek a at DDR5 pr protocol r l reveals a a di dirty little le secret… DDR5 5 bus s is s limited to 16H 16H x 32Gb 32Gb = 8H 8H x 64Gb 64Gb NRAM lik ikely to s scale to a at least 256Gb/die in in DDR5 t tim imeframe We ne need t d to correct thi his restric ictio ion n in n JEDEC
Driving Adoption of Higher Densities 27 Na Nantero i is chair o of t the J e JEDEC No Non-Vol olatil ile M Memor ory C Com ommittee Developi ping ng DDR5 5 NVRAM S Spe pecific icatio ion REXT XT ACTI TIVATE TE READ AD/WRITE TE 12 extend nded r d row bi bits ena nabl ble up up to 128Tb/ b/die die
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