NetFPGA Workshop Day 2 Presented by: Jad Naous Andrew W. Moore (Stanford University) (Cambridge University) Hosted by: Manolis Katevenis at FORTH, Crete September 16 - 17, 2010 http://NetFPGA.org Crete Tutorial – September 16-17, 2010 1 Purpose Build a complete NetFPGA design Learn: • Module creation (Verilog) • Reference pipeline integration • Verification via simulation • Verification via hardware tests • Interaction with software Crete Tutorial – September 16-17, 2010 2
Overview • Project: Cryptographic NIC • Infrastructure • Implementation • Simulation and debug • Registers • Build and test hardware • Software integration Crete Tutorial – September 16-17, 2010 3 Overview • Project: Cryptographic NIC • Infrastructure • Implementation • Simulation and debug • Registers • Build and test hardware • Software integration Crete Tutorial – September 16-17, 2010 4
Project: Cryptographic NIC Implement a network interface card (NIC) that encrypts upon transmission and decrypts upon reception Crete Tutorial – September 16-17, 2010 5 Cryptography XOR function A B A ^ B 0 0 0 XORing a 0 1 1 value with itself always 1 0 1 yields 0 1 1 0 XOR written as: ^ ⊻ ⊻ ⨁ ⊻ ⊻ ⨁ ⨁ ⨁ XOR is commutative: (A ^ B) ^ C = A ^ (B ^ C) Crete Tutorial – September 16-17, 2010 6
Cryptography (cont.) Simple cryptography: – Generate a secret key – Encrypt the message by XORing the message and key – Decrypt the ciphertext by XORing with the key Explanation: (M ^ K) ^ K = M ^ (K ^ K) Commutativity = M ^ 0 A ^ A = 0 = M Crete Tutorial – September 16-17, 2010 7 Cryptography (cont.) Example: Message: 00111011 Key: 10110001 Message ^ Key: 10001010 Key: 10110001 Message ^ Key ^ Key: 00111011 Crete Tutorial – September 16-17, 2010 8
Cryptography (cont.) Idea: Implement simple cryptography using XOR – 32-bit key – Encrypt every word in payload with key Header Payload ⨁ ⨁ ⨁ ⨁ Key Key Key Key Key Crete Tutorial – September 16-17, 2010 9 Overview • Project: Cryptographic NIC • Infrastructure • Implementation • Simulation and debug • Registers • Build and test hardware • Software integration Crete Tutorial – September 16-17, 2010 10
Infrastructure • NetFPGA package contents – Reusable Verilog modules – Verification infrastructure – Build infrastructure – Utilities – Software libraries • Tree structure Crete Tutorial – September 16-17, 2010 11 NetFPGA package contents • Projects: – HW: router, switch, NIC, buffer sizing router – SW: router kit, SCONE • Reusable Verilog modules • Verification infrastructure: – simulate full board with PCI + physical interfaces – run tests against hardware – test data generation libraries (eg. packets) • Build infrastructure • Utilities: – register I/O, packaging, … • Software libraries Crete Tutorial – September 16-17, 2010 12
Reusable Verilog modules Category Modules I/O interfaces Ethernet MAC MDIO CPU DMA queues PCI CPU register queues Output queues SRAM-based BRAM-based DRAM-based Output port lookup Router (CAM-based) NIC Learning switch (CAM-based) Hardwired Memory interfaces SRAM DRAM Miscellaneous FIFOs Rate limiter Generic register module Crete Tutorial – September 16-17, 2010 13 Verification infrastructure • Simulation: nf_run_test.pl – allows testing before synthesis – catches many bugs • Hardware tests: nf_regress_test.pl – test synthesized hardware • Test data generation libraries: – easily create test data: – many standard packet formats supported out of the box – easily add support for custom formats Crete Tutorial – September 16-17, 2010 14
Build infrastructure • Register system: – allocates memory to modules – generates “include” files for various languages • Build/synthesis: – required shared modules documented XML (shared with register system) – shared modules pulled in during synthesis – resultant bitfile checked for timing errors Crete Tutorial – September 16-17, 2010 15 Utilities • Bitfile download: nf_download • Register I/O: regread , regwrite • Device querying: nf_info • SRAM dumping: lib/scripts/sram_dump Crete Tutorial – September 16-17, 2010 16
Software libraries • Libraries for interfacing with NetFPGA: – C, Perl, Java, partial Python support Crete Tutorial – September 16-17, 2010 17 Tree Structure (1) netfpga bin (scripts for running simulations and setting up the environment) bitfiles (contains the bitfiles for all projects that have been synthesized) lib (shared Verilog modules, libraries needed for simulation/synthesis/design) projects (user projects, including reference designs) Crete Tutorial – September 16-17, 2010 18
Tree Structure (2) lib C (common software and code for reference designs) java (contains software for the graphical user interface) Makefiles (makefiles for simulation and synthesis) (libraries to interact with reference designs, create Perl5 test data, and manage simulations/regression tests) python (common libraries to aid in regression tests) (utility scripts – less commonly used than those in scripts the bin directory) verilog (modules that can be reused in designs) Crete Tutorial – September 16-17, 2010 19 Tree Structure (3) projects/crypto_nic doc (project specific documentation) (XML files defining project and any local modules, include auto-generated Verilog register defines) lib (C/Perl defines for registers) regress (regression tests to test generated bitfiles) (non-library Verilog code used for synthesis and src simulation) sw (software elements of the project) (project-specific .xco files to generate cores, synth Makefile to implement the design) verif (simulation tests) Crete Tutorial – September 16-17, 2010 20
Overview • Project: Cryptographic NIC • Infrastructure • Implementation • Simulation and debug • Registers • Build and test hardware • Software integration Crete Tutorial – September 16-17, 2010 21 Getting started with a new project (1) • Projects: – Each design represented by a project – Location: netfpga/projects/<proj_name> • netfpga/projects/crypto_nic – Consists of: • Verilog source • Simulation tests • Hardware tests • Libraries • Optional software Crete Tutorial – September 16-17, 2010 22
Getting started with a new project (2) – Normally: • copy an existing project as the starting point – Today: • pre-created project – Missing from pre-created project: • Verilog files (with crypto implementation) • Simulation tests • Hardware tests • Custom software Crete Tutorial – September 16-17, 2010 23 Getting started with a new project (3) Typically implement ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� functionality in one or more modules inside ������������� the user data path ������������������ User data ������ path ������������� Crypto module to encrypt and decrypt packets ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� Crete Tutorial – September 16-17, 2010 24
Getting started with a new project (4) – Shared modules included from netfpga/lib/verilog • Generic modules that are re-used in multiple projects • Specify shared modules in project’s include/project.xml – Local src modules override shared modules – crypto_nic: Local Shared user_data_path.v Everything else crypto.v Crete Tutorial – September 16-17, 2010 25 Exploring project.xml (1) • Location: project/<proj_name>/include <?xml version="1.0" encoding="UTF-8"?> <nf:project …> Short name <nf:name>Crypto NIC</nf:name> Description <nf:description>NIC with basic crypto support</nf:description> <nf:version_major>0</nf:version_major> Version information <nf:version_minor>1</nf:version_minor> • indicate bitfile version <nf:version_revision>0</nf:version_revision> <nf:dev_id>0</nf:dev_id> Unique ID to identify project See: http://netfpga.org/foswiki/bin/view/NetFPGA/OneGig/DeviceIDList Crete Tutorial – September 16-17, 2010 26
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