Model-Gra*: Accurate, Scalable and Flexible Analysis of Cache - PowerPoint PPT Presentation

Michele TORTELLI Dario ROSSI Emilio LEONARDI Model-Gra*: Accurate, Scalable and Flexible Analysis of Cache Networks 23rd ICNRG MeeIng (Interim) – 14/15-01-2016 michele.tortelli@telecom-paristech.fr

M OTIVATION Simula2on is the primary tool for performance evaluaIon of cache networks. Some phenomena only appear @ scale… 4-level Binary Tree Constant C/M = 0.1%, Zipf’s α = 1, IRM 35 25 P hit C / 75-th percentile 30 20 25 C/75-th percentile 15 20 P hit [%] 15 10 10 5 5 0 0 |Cache| (C) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 1e9 |Catalog| (M) 1e5 1e6 1e7 1e8 1e9 1e10 1e11 1e12 Web catalog size esImate [1] (opImisIc) [1] K. PenIkousis et al., InformaIon-centric networking: EvaluaIon methodology, Internet Dra* - (Oct. 2015) 2/9

S IMULATION L IMITATIONS People have limited CPU & Memory budgets ccnSim v0.3 ccnSim v0.4-alpha 35 25 P hit C / 75-th percentile 30 20 25 C/75-th percentile 15 20 P hit [%] 15 10 10 5 5 0 0 |Cache| (C) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 1e9 |Catalog| (M) 1e5 1e6 1e7 1e8 1e9 1e10 1e11 1e12 CPU = 1.2 h Memory = 2.15 GB 3/9

S IMULATION L IMITATIONS People have limited CPU & Memory budgets ccnSim v0.3 ccnSim v0.4-alpha 35 25 P hit C / 75-th percentile 30 20 25 C/75-th percentile 15 20 P hit [%] 15 10 10 5 5 0 0 |Cache| (C) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 1e9 |Catalog| (M) 1e5 1e6 1e7 1e8 1e9 1e10 1e11 1e12 CPU = 1.2 h Memory = 2.15 GB CPU = 1.1 h Memory = 673 MB 3/9

S IMULATION L IMITATIONS People have limited CPU & Memory budgets ccnSim v0.3 ccnSim v0.4-alpha 35 25 P hit C / 75-th percentile 30 20 25 C/75-th percentile 15 20 P hit [%] 15 10 10 5 5 0 0 |Cache| (C) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 1e9 |Catalog| (M) 1e5 1e6 1e7 1e8 1e9 1e10 1e11 1e12 CPU = 1.2 h Memory = 2.15 GB CPU = ~ 1/2 day Memory = 6.8 GB CPU = 1.1 h Memory = 673 MB 3/9

S IMULATION L IMITATIONS People have limited CPU & Memory budgets ccnSim v0.3 ccnSim v0.4-alpha 35 25 P hit C / 75-th percentile 30 20 25 C/75-th percentile 15 20 P hit [%] 15 10 10 5 5 0 0 |Cache| (C) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 1e9 |Catalog| (M) 1e5 1e6 1e7 1e8 1e9 1e10 1e11 1e12 CPU = ~ 5 days Memory = 68 GB CPU = ~ 1/2 day Memory = 6.8 GB One order of magnitude more becomes resource expensive 3/9

S IMULATION L IMITATIONS People have limited CPU & Memory budgets ccnSim v0.3 ccnSim v0.4-alpha 35 25 P hit C / 75-th percentile 30 20 25 C/75-th percentile 15 20 P hit [%] 15 10 CPU = ~ 50 days 10 5 Memory = 680 GB 5 0 0 |Cache| (C) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 1e9 |Catalog| (M) 1e5 1e6 1e7 1e8 1e9 1e10 1e11 1e12 CPU = ~ 5 days Memory = 68 GB CPU = ~ 1/2 day Memory = 6.8 GB Two orders of magnitude more become really cumbersome 3/9

S IMULATION L IMITATIONS People have limited CPU & Memory budgets ccnSim v0.3 ccnSim v0.4-alpha 35 25 P hit C / 75-th percentile CPU = > 1 year 30 20 Memory = ~ 7 TB 25 C/75-th percentile 15 20 P hit [%] 15 10 CPU = ~ 50 days 10 5 Memory = 680 GB 5 0 0 |Cache| (C) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 1e9 |Catalog| (M) 1e5 1e6 1e7 1e8 1e9 1e10 1e11 1e12 CPU = ~ 5 days Memory = 68 GB CPU = ~ 1/2 day Memory = 6.8 GB Three orders of magnitude more become unfeasible 3/9

S IMULATION L IMITATIONS People have limited CPU & Memory budgets ccnSim v0.3 ccnSim v0.4-alpha 35 25 P hit C / 75-th percentile CPU = > 1 year 30 20 Memory = ~ 7 TB 25 C/75-th percentile 15 20 P hit [%] 15 10 CPU = ~ 50 days 10 5 Memory = 680 GB 5 0 0 |Cache| (C) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 1e9 |Catalog| (M) 1e5 1e6 1e7 1e8 1e9 1e10 1e11 1e12 CPU = ~ 5 days Memory = 68 GB CPU = ~ 1/2 day Memory = 6.8 GB Require careful instrumentaIon Event-driven Simula2on à Massive compuIng power at large scale Inefficient (wasIng Ime and memory with expected events) 3/9

I DEA GAIN Time to Live (TTL) caches CPU & Memory Downscaling M, C, and R with factor Δ CPU & Memory RejecIon Inversion Sampling Memory Error correcIon with feedback loop Stability & Accuracy Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on 4/9

I DEA GAIN Time to Live (TTL) caches CPU & Memory Downscaling M, C, and R with factor Δ CPU & Memory RejecIon Inversion Sampling Memory Error correcIon with feedback loop Stability & Accuracy Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on 4/9

I DEA GAIN Time to Live (TTL) caches CPU & Memory Downscaling M, C, and R with factor Δ CPU & Memory RejecIon Inversion Sampling Memory Error correcIon with feedback loop Stability & Accuracy Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on 4/9

I DEA GAIN Time to Live (TTL) caches CPU & Memory Downscaling M, C, and R with factor Δ CPU & Memory RejecIon Inversion Sampling Memory Error correcIon with feedback loop Stability & Accuracy Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on 4/9

I DEA GAIN Time to Live (TTL) caches CPU & Memory Downscaling M, C, and R with factor Δ CPU & Memory RejecIon Inversion Sampling Memory Error correcIon with feedback loop Stability & Accuracy Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on Ex. with Δ=1e5 ~ 100x CPU & Memory gain ~ 2% Accuracy 4/9

U NDER THE H OOD T C guess S CENARIO R ESULTS D ESCRIPTION Model MC-TTL SimulaIon T C Topology Downscaling factor (Δ) Yora (Y) RouIng and Forwarding Cache Replacement Policy Cache Decision Policy Content popularity Catalog cardinality (M) Cache size (C) Number of requests (R) 5/9

U NDER THE H OOD T C guess S CENARIO R ESULTS D ESCRIPTION Model MC-TTL SimulaIon T C Topology Downscaling factor (Δ) Yora (Y) RouIng and Forwarding Cache Replacement Policy Cache Decision Policy Content popularity Catalog cardinality (M) M M’ = M / Δ Downscaled catalog D OWNSCALING Cache size (C) C C T = C / Δ Target cache & S AMPLING Number of requests (R) Δ R’ = R / Δ Dowscaled # events R Backup slides for technical details 5/9

R ESULTS I – V ERY L ARGE S CENARIO 4-level Binary Tree |Cache| - C = 1e6 |Catalog| - M = 1e9 Downscaling Factor - Δ = 1e5 # Requests - R = 1e9 Cache Decision Policy P hit CPU | Gain Mem [MB]| Gain SimulaIon 33.2 11.4 h 6371 LCE 160x 168x MC-TTL 31.4 256 s 38 SimulaIon 35.4 7.3 h 6404 FIX0.1 90x 168x MC-TTL 34.0 291 s 38 SimulaIon 37.0 10.8 h 8894 2-LRU 97x 234x MC-TTL 36.1 402 s 38 6/9

R ESULTS II – W EB S CALE S CENARIO 1.2*10 6 Memory Model FiUng (Simulator) 1.8E+11 1 TB 1.6E+11 1.0*10 6 1.4E+11 8.0*10 5 1.2E+11 Mem = (1.65 10 -4 ) N C + 4 10 -6 M + 19.83 [MB] 512 GB 1.0E+11 6.0*10 5 (ccnSim v0.4-alpha with rejecIon inversion sampling) 8.0E+10 4.0*10 5 6.0E+10 2.0*10 5 4.0E+10 64 GB 1 cache entry ≈ 165 Bytes ● 2.0E+10 0.0*10 0 1 catalog entry = 4 Bytes ● M 20 40 60 80 100 120 140 160 180 200 N Fix cost ≈ 19.83 MB ● CDN-like: N~60 - M=1e11 - C=1e7 Technique MC-TTL SimulaIon (Est) Mem[MB] CPU Cycles Mem[MB] CPU 4-level Parameters M=R=1e10 - C=1e6 - Δ=1e5 45 0.4 h 1 70000 4.7 days Binary Tree CDN-like M=R=1e11 - C=1e7 - Δ=1e6 31 12.5 h 3 520000 ~ 50 days (N=67) 7/9

C ONCLUSIONS Extreme scalability, general methodology Implementable in every simulator (ndnSIM, Icarus, …) Available in ccnSim v0.4-alpha (hrp://perso.telecom-paristech.fr/~drossi/ccnSim) Technical Report (slightly old) M. Tortelli, D. Rossi and E. Leonardi, Model-Gra*: Accurate, Scalable and Flexible Analysis of Cache Networks Tech. Rep . [CCN-TR15], Telecom ParisTech, 2015. 8/9

THANK YOU QUESTIONS 9/9

BACKUP SLIDES

C HE ’ S A PPROXIMATION T C (m) = T C Cache evic)on )me for content m (i.e., interval of Ime a*er which ‘m’ is evicted) Assumed to be CONSTANT , independent from the content

U NDER THE H OOD T C guess S CENARIO R ESULTS D ESCRIPTION MC-TTL SimulaIon Model T C I NITIALIZATION MC-TTL S IMULATION C YCLE C T T C (z+1) D OWNSCALING MC-TTL C ONTROLLER : S TABILITY & S AMPLING S IMULATION T C C ORRECTION C HECK C M (z) C ONSISTENCY C HECK

D OWNSCALING & S AMPLING M M’ = M / Δ Downscaled catalog D OWNSCALING & S AMPLING C C T = C / Δ Target cache Δ R R’ = R / Δ Dowscaled # events . . . 1 2 3 M’ META CONTENTS . . . 1 2 3 M’ BINS NOT SCALABLE! Requested with probability M’ Ο(Δ) init cost Meta content Δ contents of the n-th bin M’ Ο(Δ) space cost n-th bin Ο(logΔ) sampling Ime Rejec2on Inversion Sampling ( VERY SCALABLE!) Extract Zipf’s distributed random numbers between [1, Δ] No Memory and Ο(1) runIme complexity

S TABILITY C HECK Pivotal role to simulate the R’ (1) requests at steady state Dynamic transient period Adap2ve Stability Monitor (rouIng, meta-caching, topology,…) Coefficient of VariaIon ( CV ) of the mean hit probability ( CV = std(p hit ) / E(p hit ) ) Batch mean of W samples (new sample iif acIve cache and state change) Check stability (i.e., CV < 5 10 -3 ) for the first N’ = Y N nodes, where Y ∈ ]0,1]. (1) ED-Sim: end = R / (Λ*Cl), with MC-TTL: end’ = R’ / (Λ’*Cl), with Since end = end’ à R’ = R / Δ