Model Based Estimation for Mixed Signal System A guide to design - PowerPoint PPT Presentation

Model Based Estimation for Mixed Signal System A guide to design first time Optimization correct systems Sumit Adhikari and Jörg Kock System Architecture and Innovation BL Sensors, BU Automotive Hamburg, Germany

Overview: Agenda  Learning a top-down design methodology through which first time success is possible What will be told  What to do in terms of methodology and design flow What will be not told  How to do (specially in connection to modelling and detailed design) Assumption  Everybody in my audience is a SystemC-AMS / COSIDE user  I do not need to speak about the motivation of using it 2. November 17, 2015

What is I am going to talk in 20mins! Requirement Analysis (SysML/UML/IBM-DOORS) Algorithm Design (C/C++/MATLAB) Business Case Maintenance Acceptance Requirements Testing Analog/RF Digital Software Architecture Architecture Architecture (SystemC-AMS) (SystemC) (C/C+) System System Specification Verification Integration Circuit Design RTL Design SW Development System Design (Spice/Spectre) (Verilog/VHDL) (C/C++) Validation Component Unit Testing Design Analog Layout Digital Layout Implementation GDSII 3. November 17, 2015

The Problem You See As - Voltage Oscillator Regulator A D BG POR A D Processor ISS Memories Software A D HW Accelerator Clock and Peripheral Reset Management 4. November 17, 2015

The Problem You are Actually Dealing With!! Supply Settling, bandwidth ripple jitter, duty suppression cycle Gain Adaptive ? , settling Oscillator Voltage Regulator Slew rate A D Filter type, Noise coefficient figure Settling BG POR Supply ripple Offset Switch suppression, settling output voltage Registers/ behav, settling Addresses ? Gain non- Processor family, linearity memory hierarchy, A D CMRR Processor IiSnSterrupt, WDT, Supply Continuous cache? saturation FIFO ? Refinement until best system is achieved PSRR mismatches Clock Memories Software Size, jitter type, loading D speed A Thermal HW Accelerator noise Linearization, Calibration, 1/f noise Clock and Reset Peripheral Offset cancellation, Management Bus mismatch analysis bandwidth, 5. November 17, 2015 delay

Top down design refinement flow – Steps (1)  Algorithm Design Requirement Analysis (SysML/UML/IBM-DOORS)  Find the algorithm and all “algorithmic parameter” using MATLAB. Algorithm Design (C/C++/MATLAB)  Architecture Level Design (Level I)  Implement the architecture from algorithm in SystemC-AMS Analog/RF Digital Software Architecture Architecture Architecture (SystemC-AMS) (SystemC) (C/C+) + SystemC  Algorithm refinement using transfer functions, switches, Circuit Design RTL Design SW Development (Spice/Spectre) (Verilog/VHDL) (C/C++) passives, accurate regulation loop, thermal noise, 1/f noise and non-idealities (small and large signal both). Analog Layout Digital Layout  Co-simulate and optimize the architecture level design GDSII 6. November 17, 2015

Top down design refinement flow – Steps (7) Requirement Analysis (SysML/UML/IBM-DOORS)  Design optimization and design centering (Level II)  Talk to process team for passive components and model Algorithm Design (C/C++/MATLAB) them.  Characterize closest possible available active components and include characterized behavior in your model. Do not Analog/RF Digital Software Architecture Architecture Architecture (SystemC-AMS) (SystemC) (C/C+) forget to fit temperature variations.  Co-simulate and optimize the design for parameters Circuit Design RTL Design SW Development (Verilog/VHDL) (Spice/Spectre) (C/C++)  Design for reliability and robustness (Level III) Analog Layout Digital Layout  Perform 5 sigma Monte Carlo to prove the design.  Apply extensive failure injection and analysis  If MC or failure analysis fails, re-optimize system architecture GDSII 7. November 17, 2015

Temperature Sensor, An Example – Algorithm (The MATLAB)  The world of MATLAB ends here. doubleTo Data Fit  More you struggle with speed, less PTAT s16 Algorithm you analyze.  Focus more on full system design and optimization. Data Fit ADC  You are correct – you cannot reuse PTAT Algorithm Algorithm or extend what you did till now! 8. November 17, 2015

Temperature Sensor, An Example – Architecture (SystemC(-AMS) Starts Here) Quantizer is clocked  Be careful about the characterization results you are getting VSUP Vreg PTAT Data Fit g m Quant CIC Algorithm  Delay the implementation phase as much as possible, get all analysis Oscillator done here before the design starts.  Reuse is not always the very intriguing idea.  Do not over specify and do not let overdesign. More complex than shown here 9. November 17, 2015

Get some feeling on modulator Internals! intOut(Volts) 1.5 2 intOut(Volts) 1 1 0.5 0 1.305 1.31 1.315 1.32 1.325 1.33 1.335 1.34 1.345 1.35 1.355 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 -4 Time (Sec) -4 Time (Sec) x 10 x 10 dacOut(Volts) 2 dacOut(Volts) 2 0 0 -2 -2 1.305 1.31 1.315 1.32 1.325 1.33 1.335 1.34 1.345 1.35 1.355 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 Time (Sec) -4 -4 Time (Sec) x 10 x 10 sdmOut(logic) 1 sdmOut(logic) 1 0.5 0.5 0 0 1.305 1.31 1.315 1.32 1.325 1.33 1.335 1.34 1.345 1.35 1.355 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 -4 Time (Sec) -4 Time (Sec) x 10 x 10  Effect of OPAMPs and Switches are clearly seen, check for track and hold 10. November 17, 2015

Sensor Behaviour and Algorithmic Error after Poly-Fit Real vs Ideal PTAT Output Behaviour Temperature Error after fitting 1.4 0.12 1.2 0.1 1 0.08 0.8 Output Voltage PTAT Error(%) 0.6 0.06 0.4 0.04 0.2 0.02 0 -0.2 0 0 100 200 300 400 500 600 200 250 300 350 400 450 500 Temperature Temperature 11. November 17, 2015

Error Output from System Temperature Error Plot Temperature Error Plot 4.5 1 4 0.9 3.5 0.8 Temperature Error in Percentage Temperature Error in Degrees 0.7 3 2.5 0.6 2 0.5 1.5 0.4 1 0.3 0.5 0.2 0 0.1 -50 0 50 100 150 200 -50 0 50 100 150 200 Temperature Temperature 12. November 17, 2015

Error Output from System (In presence of power supply ripple) Temperature Error Plot Temperature Error Plot 1.4 2 PS Ripple 1MHz PS Ripple 1KHz 1.95 1.2 square wave square wave 1.9 Temperature Error in Percentage Temperature Error in Percentage 1 1.85 1.8 0.8 1.75 0.6 1.7 1.65 0.4 1.6 0.2 1.55 0 1.5 -50 0 50 100 150 200 -50 0 50 100 150 200 Temperature Temperature 13. November 17, 2015

Monte Carlo Simulation (Before and After Further Optimization) Monte Carlo of Temperature Error Plot with 5 σ process variation Monte Carlo of Temperature Error Plot with 5 σ process variation 1.4 1 0.9 1.2 0.8 Temperature Error in Percentage Temperature Error in Percentage 1 0.7 0.6 0.8 0.5 0.6 0.4 0.3 0.4 0.2 0.2 0.1 0 0 -50 0 50 100 150 200 -50 0 50 100 150 200 Temperature Temperature 14. November 17, 2015

COSIDE / SystemC-AMS Improvement Requests  ELN MoC Improvements :  ELN Noise sources (voltage & current),  abstract ELN transfer functions and saturation elements (current & voltage),  slew rate,  temperature dependent ELN primitives  temperature behaviour spec for abstracts.  Pole Zero (Stability) analysis – Complex Plane notation should be fine.  Multicore SystemC-AMS – analog solver for speed improvement 15. November 17, 2015 COMPANY CONFIDENTIAL

Summary and Conclusion  We presented a flow using which  Accurate DS can be extracted at earliest phase of development.  Feasibility of the system, complete behavior of the system is well understood at the earliest phase.  Cost reduction using few architects instead of entire design team experimenting over spins.  No re spins due to lack of understanding.  Outlook  Engaging most of the activities during Architecture phase (using SystemC-AMS + SystemC) is highly beneficial and the correct direction to follow.  Additional COSIDE and/or SystemC-AMS features in the area of ELN MoCs and Analysis appreciated to further improve our design flow 16. November 17, 2015

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