Manufacturing Challenges and their Implications on Design Phi - PowerPoint PPT Presentation

Manufacturing Challenges and their Implications on Design Phi Phiroze Parakh, Ph.D P kh Ph D

45nm/32nm Design Challenges MANUFACTURING PROCESS & DESIGN VARIATIONS VARIATIONS LOW POWER LOW POWER LARGE DESIGNS

The Evolution of Signoff EOUT PRE-TAPE P 32nm 130nm 90nm 65nm 45nm DRC DRC DRC DRC Critical Feature C C Critical Feature Critical Feature C Analysis Analysis Analysis Critical Area Critical Area Analysis Analysis Litho-friendly Lith f i dl Litho-friendly Lith f i dl Design Design Litho-aware Silicon Modeling

Variability vs. Yield, Cause vs. Effect Variability: spread in process/layout parameters and is � inherently caused by the litho-process Yield: measure of success-rate in fabrication process � Yi ld f il Yield-failure: limiting case of variability. li iti f i bilit � The effect of a high- σ event!

P&R, RET and Fabrication timing place opt route clock logic P&R P&R GDS2 GDS2 Corners Gate delays RC/µm RC/µm “RET: Backend” “RET: Backend” OPC OPC CAA CAA LFD LFD Design rules Litho model Mask Layer Mask Lay ers Parametric Variations Defect densities Defect densities yield wafer models “FAB: Tapeout” Design rules

How does robust optimization address variability? fast RC low V th Typical optimization Typical optimization centered around nominal Fab & Test Universe process high V th slow RC slow RC Robust optimization seeks to cover larger process conditions Robust optimization seeks to cover larger process conditions p p g g p p

Taxonomy Parametric (process) Systematic y Spatial (wafer/die) p ( ) Proximity (local position) Temperature/Voltage Variability Dynamic N.B.T .I Electro-migration Particle Defects Random Random I Implant l t L.E.R What can be addressed by P&R? What can be addressed by P&R? What can be addressed by P&R? What can be addressed by P&R?

Example → Systematic Parametric Variation: PV-Bands The bands The bands represent a range of M3 simulations across Dose, across Dose Defocus, and V23 Mask-Bias M2 Drawn != Actual Drawn != Actual Olympus Calibre LFD

Understanding Lithography is the first step Mask Wafer λ NA: sin( θ ) Resist Critical_dimension = κ 1 * λ / Numerical_Aperture

How is sub- λ possible? λ = 193nm; sin( θ ) ≤ 1 → CD ≥ 193nm � CD = k 1 * λ /NA 1.35 1.35 • NA can be > 1 if we use immersion lithography 1.2 • η η water = 1 31 1.31 t 0.92 0.85 • NA Take advantage of the mask-spectrum • • Partially coherent imaging Partially coherent imaging κ 1 κ 1 • Off-axis illumination 0.62 • Annular light sources 0.48 0.44 0.35 0.24 • Improve the mask via OPC 90nm 65nm 45nm 32nm 22nm

Optics: Initial Source of Variability Mask Resist Wafer 1.1 E 0 0.9 E 0 Exposure Latitude Mask Bias Focus σ (CD image ) limits σ (E 0 ) σ (DOF) limited by σ (CD image ) σ (CD image ) limits σ (CD mask ) The variance of CD image , Exposure, Masks and Focus are coupled

Parametric Variability in Lithography space Fat M1 Variabil Variability ty is a is a measure of the change in the image measure of the change in the image over changes over changes in in Dose Dose, , Focus Focus and and Mask-Bias Mask-Bias

Variability through Timing Corners Inverter driving 25µm of M2 250 200 150ps s) 150 150 Delay (ps Weak: High-Vt 100 Weak: Low-Vt 50 20ps Strong: High-Vt Strong: Low-Vt Strong: Low-Vt 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 Corners 1.2v, 0 ° C, best RC 1 2 0 ° C b t RC 0.9v, 125 ° C, worst RC 0 9 125 ° C t RC Each corner is a full chip timing → tighten the range Each corner is a full chip timing → tighten the range

Robust P&R for DFM place opt route clock logic Timing Timing aw awar are Multi-corner analysis Litho Errors Litho Errors Advanced Rules Metal Fill CAA / Yield Fast DRC Mentor Olympus DB CMP Maps Wire Spreading p g Double Via Ins. Litho Litho aw awar are Litho analysis CAA LFD OPC CMP

Parametric (process) Systematic y Spatial (wafer/die) p ( ) Proximity (local position) Temperature/Voltage Variability Dynamic N.B.T .I Electro-migration Particle Defects Random Random I Implant l t L.E.R

S Systematic vs. Parametric 80nm 80nm 65nm 65nm Actual Shape Can be Simulated Systematic → Drawn - Actual Systematic → Drawn - Actual 85nm? 85nm? Parametric → σ (Actual) 120nm? 120nm? 69nm? 69nm? 60nm? 60nm? 64nm? 64nm? Can we account for Drawn Shapes in Routing? Can we account for Drawn Shapes in Routing? Can we account for Drawn Shapes in Routing? Can we account for Drawn Shapes in Routing?

S Metal Pinching (Min-Width) M2 bridge with litho error Pinched (but still ok) PV-band violation OPC: nominal case Rather than make Rather than make Rather than make Rather than make Rather than make Rather than make Rather than make Rather than make OPC solve for all OPC solve for all OPC solve for all OPC solve for all Process windows, Process windows, Process windows, Process windows, we could make the we could make the we could make the we could make the M2 M2 jog M2 M2 jog jog wider jog wider wider wider

S Density based width variation 40nm 20nm variation! 60nm Modeled in Modeled in Modeled in Modeled in RC extraction RC extraction RC extraction RC extraction RC extraction RC extraction RC extraction RC extraction

S Double vias can be a double edged sword 80nm 39nm 43nm Increased Increased contact reliability Increased Increased contact reliability contact reliability � Decreased contact reliability � Decreased Decreased metal reliability Decreased metal reliability metal reliability metal reliability

S Locality != adjacency Space allows the other side the other side to compensate Symmetry Symmetry suggests this should be an error M3 min-width i idth violation

S Robust repair of Litho-Errors Aggressor Zones Zones Expand to fix error Victim Rotate (if possible) Use a fine grid to resolve violation

S Systematic vs. Parametric 80nm 80nm 65nm 65nm Actual Shape Can be Simulated Systematic → Drawn - Actual Systematic → Drawn - Actual 85nm? 85nm? Parametric → σ (Actual) 120nm? 120nm? 69nm? 69nm? 60nm? 60nm? 64nm? 64nm? Can we account for Drawn Shapes in Timing? Can we account for Drawn Shapes in Timing? Can we account for Drawn Shapes in Timing? Can we account for Drawn Shapes in Timing?

S OCV → Margins → “Fudge-factor” � “OCV Margin” factor of ~20% � This factor masks This factor masks � Location based variation � L/Weff variation � IR-drop etc.. � Robust OCV → model each factor

S Systematic Density-based Variation for a Timer 65nm 65nm Low density 45nm 45nm l diameter 32nm 32nm High density High density Optical High cell density → increased σ (L eff ) High cell density → increased σ (L eff ) Proximity(Density) Based OCV Proximity(Density) Based OCV

S Parasitic Variation and Chemical Mechanical Polishing Wire thickness (C lateral ) is a function of layer, density and width The dielectric between layers will also vary → σ (C substrate ) Per layer CMP variation → M3 could be worse than M2! y Metal fill makes density consistent Calibre CMP

Taxonomy Parametric (process) Systematic y Spatial (wafer/die) p ( ) Proximity (local position) Temperature/Voltage Variability Dynamic N.B.T .I Electro-migration Particle Defects Random Random I Implant (V th ) l t (V ) L.E.R

Dynamic Variation D � Time/state dependent � Eg: Negative Bias Temp Instability (NBTI) max V max V th When will we reach max Vth? 125 ° h ) log(V th 25 ° log(t) Lifetime “ A comprehensive model of PMOS NBTI degradation ”, M. Alam. � A ° K map + target conditions are needed A ° K + t t diti d d � Also supports delay dependence on IR-drop

Taxonomy Parametric (process) Systematic y Spatial (wafer/die) p ( ) Proximity (local position) Temperature/Voltage Variability Dynamic N.B.T .I Electro-migration Particle Defects Random Random I Implant (V th ) l t (V ) L.E.R

Random variation along timing-path R � σ (V th ) = K ⁄ √ W·L Due to variation in number and distribution of dopant p � atoms in the channel logic_path_depth: 5 l i th d th 5 0.78v 0.58v clock_path_depth: 2 σ (logic): σ (V th )* √ 5 σ (clock): σ (V th )* √ 2 Different distribution! Same number of atoms On clock trees, even a small difference in path-depth matters. On clock trees, even a small difference in path-depth matters. “Random dopant induced threshold voltage lowering and fluctuations” , Asen Asenov.

Random Fault: Critical Area Analysis R ∞ C.A = ∫ P(r) · A(r) dr 0

CAA: How is A(r) to be determined? R Shorts: PV-Bands → 3 possible A(r) Opens: Opens: PV-Bands → 3 possible A(r) Conservative: Inner band for opens and Outer band for shorts Conservative: Inner band for opens and Outer band for shorts

Improving CAA score R C.A = ∫ P(r) · A(r) dr ∫ ∞ 0 Tough to spread! Easier Impr Impr prove prove ove A(r) ove A(r) A(r) by w A(r) by w wire-spr wire-spr -spreading o -spreading o eading or w eading or w wire-si wire-si -sizing -sizing ing ing