LIU – SPS Low level RF Slip stacking implementation Arthur Spierer, 18.04.2018
SPS LLRF overview coaxial f C,ext ΔT(f rev , f C ext ) TDC Fibers to/from CPS 1.25Gbps Beam Control B-field WR Fibers to/from LHC SPS f RFext coaxial ADC ΔΦ( RF, RF ext ) WR Fibers to kickers RF-Synchro Switch Fibers to BA2 2 >4Gbps I beam , CPS RX f rev φ beam I beam RF-synchro Σ Vcav >4Gbps f RF WR dV, dP δ R beam RX WR F RF, EXT F C, EXT 1.25Gbps RX Ref magnet F REVinj FTWs, Setpoints 8x WR TX B-field F RFinj WR RF Diagnostic >5Gbps WR Master clock RF Obs triggers 10MHz Switch (BQM, MR, ...) f rev 8 f RF WR ≥ 13 4 Surface building BA3 RX RX RX RX RX RX TX WR WR WR WR WR TX WR TX TX TX TX TX TX 2x (faraday cage) Cavity Cavity Cavity Cavity Radial Beam Controller Controller Controller Controller position phase TX TX IOT IOT Surface building BA3 coaxial coaxial Coaxial line coaxial Coaxial line coaxial coaxial coaxial waveguide waveguide cable SPS Tunnel Σ Σ Σ Σ Beam Radial Phase TWC800 TWC800 TWC200 TWC200 WCM Pick-up(s) Pick-up(s) 6x
Beam control Hardware overview Cavity Beam Cavity Beam WR B WR RF Controllers Phase/Pos. network network Controllers Phase/Pos. 16 SFP+ RTM QSFP QSFP QSFP SFP SFP SFP SFP RTM eRTM «LO» PLL clock Cleaning Zynq PLL AMC White-rabbit 4x ADC receiver Digital I/O’s 125Msps FMC FMC External External RF AFCZ FMC Carrier Timings F common 400 MHz
Cavity controller overview DS8VM1 (Desy/Struck) SIS8300-KU (Desy/Struck)
Beam Control Beam Control AFCZ 8x Cavity Vcav controlers dV, dP dV, dP Longitudinal Φbeam damper Vcav Φbeam Beam phase Blow up ΔFTW noise noise Backplane Timing CTRx LVDS Beam radial dR position Vcav IQ ΔFTW rev,phase, b1-2 Φbeam Phase loop Serial links Φs Φ H1, b1-2 FTWs Σ F RF, External NCO Φ H1, prog, b1-2 distribution F RF,ext Frev b1-2 dR prog ΔFTW rev,radial dR RF RF Radial loop FTWs ADC FMC White Rabbit WR switch Fc, Frev Fc V ca distribution v[0..7] Φ ca Function v[0..7] generator dR prog Φ H1 ΔFTW rev,sync, b1-2 Synchro loop Φ H1,prog Digital I/O FMC Timings Φbeam CTRx ΔΦ RF,RFext ΔT Fc,Frev Legend B-train Frequency Memory Map FTW rev,prog, b1-2 B, B dot White Rabbit program Hardware unit dR prog Φs B-train FPGA firmware WR switch FPGA CPU
Beam Control Slip Stacking • Slip Stacking is part of the frequency program • Frequency and voltage ramps are computed in real-time or recorded • Two phase loops and synchro loops during Slip Stacking • Bunch by bunch phase measurement for each super-batch • NCOs are synchronised and updated through White-Rabbit Beam Control AFCZ Cavity controller group 1 Cavity controller Cavity controller group 1 group 1 AM Φ H1, b1 RF FTW delayed FTW delayed NCO White Rabbit Φ H1, b1-2 Frev b1 Vcav IQ NCO Serial links Φ H1, prog, b1-2 ΔFTW rev,phase, b1-2 Φbeam Φbeam Phase loop Frev b1-2 Beam phase Φs Φ H1 , b1-2 ΔFTW rev,sync, b1-2 RF RF FTW Φ H1,prog , b1-2 Synchro loop Cavity controller group 2 Cavity controller White Rabbit WR switch Cavity controller Φbeam FTW Σ group 1 group 1 AM RF Φ H1, b1 FTW delayed Legend NCO B-train B-train Frequency FTW rev,prog, b1-2 B, B dot White Rabbit Hardware unit Frev b1 WR switch White Rabbit program Φ H1, b1-2 FPGA firmware FPGA CPU
Frequency Program Slip Stacking • Ramps are computed (real time or recorded) based on parameters • Maximum slope, Target frequency, Maximum frequency offset, … • The slippage can be monitored in real time for the two super-batches • Allows detection of the recapture time Frequency Program dF target, dF max, dF max_slope Φ H1, b1-2 Slip Stacking ΔF slip,b1-2 F target, dF max, dF max_slope, µ pll ΔF reph. Rephasing ΔΦ RF,RFext ΔT Fc,Frev Frev Fprog m/q , γ t, R SPS, H SPS, F inf FTW rev FTW rev, prog, b1-2 B to Frev B dR prog Trans cross Stable Phase B dot Φs V rf
Real time computation • Allows a turn by turn resolution without interpolation • Straight forward for frequency, to be studied for voltage Slip Stacking ΔΦ slip done Sequencer start slip Φ H1, b1-2 dF target, dF max mode , dF max_slope constants parameters Ramp ΔF slip,b1-2 t FTW rev_prog T rev_prog Timer Frev b1-2
Frequency trim function candidate • SPS Rephasing trim function f D f/2 slope a 4 3 2 a - D t/2 3 t f ( t ) a . t t = − D t/2 3 2 3 f Δ - D f/2 • Trim functions are symmetrical for each cavity group
Voltage trim function • Voltage function is Derived from the frequency ramp and … • Meant to keep a constant bucket filling factor •
Amplitude modulation • Each cavity group RF is amplitude modulated (ON/OFF) • To separate the two super-batches injected at the same frequency • To decrease interferences between group 1 & 2 RF and batches • Once the super-batches are too close, RF is kept ON φ off2 φ on2 φ H1 Cavity group 2 RF on φ off1 φ on1 φ H1 Cavity group 1 RF on Time T fill T ba T on T ba T ba T ba T rev1
Frequency Tuning Words transmission Name Size (bits) Description • Using White Rabbit link FTW_H1 48 FTW Harmonic 1 main FTW_H1[0..7] 8x48 FTW Harmonic 1 for each cavity FTW when RF is on during Fixed frequency FTW_ON 49 Keep all nodes synchronised Acceleration (Ions) • OFFSET_H1 48 Offset on H1 phase Vcavity[0..7] 8x2x16 Cavity voltage setpoint in Amp/phase or IQ Control and status: Fixed Latency • bit 0: NCO_rst Control Status 16 bit 1: trigger capture bit 2: NCO modulation on/off One update per turn • bit 4-3: NCO modulation rate Current H1 phase in beam control for Phase_H1 48 synchronisation check
Numerically Controlled Oscillator (NCO) • Reset and updated synchronously in every nodes • Runs with the same clock on every nodes • Phase comparator for amplitude modulation FTW H1 φ H1 D Q FTW FSK H RF F REV Accumulator FTW H 1 FTW LO φ FSK,cor FTW IFavg D Q φ IFavg FTW RF,ON F IF,avg Accumulator ± FTW FSK φ IF,FSK cos(ω IF ) cordic D Q x(-1) φ FSK,cor sin(ω IF ) F FSK Accumulator Azimuth φ H1 detection nco_rst
Phase Loop • Two independent phase loops • Bunch mask for averaging on each super-batch • Stopped when batches start to superpose • Readings of the bunch per bunch phase are not coherent when the batches are superposed No phase loops • Can help defining recapture time •
LHC ion cycle
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