ECE 0142 Computer Organization Lecture 4 Arithmetic-Logic Unit 1
Arithmetic - Logic Unit ALU Handles integers Does the calculations 2
Arithmetic-Logic Unit ALU Performs arithmetic add, subtract Performs logic and, or, invert, complement Shifts right, left, arithmetic, logical Provides result and status 3
Review Binary Addition Binary Decimal Carry 1 1 1 1 0 0 0 1 1 0 1 1 2 7 1 0 1 1 0 2 2 1 1 0 0 0 1 0 4 9 4
Example Numbers 8 bit 2’s complement +127 = 01111111 = 2 7 -1 -128 = 10000000 = -2 7 16 bit 2’s complement +32767 = 011111111 11111111 = 2 15 - 1 -32768 = 100000000 00000000 = -2 15 5
Sign Extension Positive number pack with leading zeros +18 = 00010010 +18 = 00000000 00010010 Negative number pack with leading ones -18 = 11101110 -18 = 11111111 11101110 i.e. pack with MSB (sign bit) 6
Addition and Subtraction Normal binary addition circuitry Take two’s complement of subtrahend and add to minuend i.e. a - b = a + (-b) Need only addition and complement circuits 7
Consider Binary Addition Assume 5 bits 2’s complement arithmetic 12 - 7 = 12 + (-7) = 5 Binary Carry 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 Carry out 8
Consider Binary Addition Assume 5 bits 2’s complement arithmetic 12 - 13 = 12 + (-13) = -1 Binary Carry 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 1 1 1 1 Carry out 9
ALU Inputs and Outputs 10
ALU - Addition Could try this as an 8 input, 4 output combinational logic problem I nt rod uce B A b0 a 0 b3 a 3 t his n ot a tion 4 4 A d der 4 C c0 c3 C = A + B c0 = f (a 3 ,a 2 ,a 1 ,a 0 ,b 3 ,b2 ,b 1 ,b0 ) c1 = f (a 3 ,a 2 ,a 1 ,a 0 ,b 3 ,b2 ,b 1 ,b0 ) ..... c3 =f (a 3 ,a 2 ,a 1 ,a 0 ,b 3 ,b2 ,b 1 ,b0 ) 11
Instead - Consider Stages FA - Full Adder Depends on 1’s or 2’s comp arithmetic 12
Full Adder Truth Table A B C in S C S = A’B’C in + A’BC in ’ + 0 0 0 0 0 AB’C in ’ + ABC in 0 0 1 1 0 = A ⊕ B ⊕ C in 0 1 0 1 0 0 1 1 0 1 C = A’BC in + AB’C in + 1 0 0 1 0 ABC in ’ + ABC in 1 0 1 0 1 = ( A ⊕ B)C in + AB 1 1 0 0 1 1 1 1 1 1 13
Full Adder A ⊕ B A ⊕ B ⊕ C in A B C in ( A ⊕ B)C in AB ( A ⊕ B)C in + AB Graph from: Logic and Computer Design 14 Fundamentals, Mano & Kime, Prentice Hall
4 Bit Ripple Carry 2’s Complement Adder 15
Constructing an Arithmetic Logic Unit Start with a 1-Bit ALU 16
Simple Logical Operations 1. AND gate (c = a . b) a b c = a . b 0 0 0 a c 0 1 0 b 1 0 0 1 1 1 2. OR gate (c = a + b) a b c = a + b 0 0 0 a c 0 1 1 b 1 0 1 1 1 1 3. Inverter (c = a) a c = a a c 0 1 1 0 4. Multiplexor d d c (if d = = 0, c = a; 0 a else c = b) a 0 1 b c b 1 17
Starting from “AND” and “OR” Operation a 0 Result 1 b If Operation is 0, then Result = a AND b If Operation is 1, then Result = a OR b 18
Consider a 1 bit Full Adder CarryIn a Sum b CarryOut 19
With “add” Operation CarryIn a 0 If Op is 0, then Result = a AND b 1 Result If Op is 1, then Result = a OR b If Op is 2, then Result = sum of (a + b) 2 b CarryOut 20
CarryIn Operation a0 CarryIn Result0 ALU0 b0 CarryOut If we repeat the 1-Bit ALU 32 times a1 CarryIn Result1 ALU1 b1 CarryOut a2 CarryIn If Op is 0, then Res i = a i AND b i Result2 ALU2 b2 If Op is 1, then Res i = a i OR b i CarryOut If Op is 2, then Res i = sum of (a i + b i ) a31 CarryIn Result31 ALU31 b31 21
With Subtraction Binvert Operation CarryIn If Op is 0, then Res = a AND b If Op is 1, then Res = a OR b a 0 If Op is 2, and if Binvert is 0, 1 Result then Res = sum (a + b) if Binvert is 1, 0 b 2 then Res = sum (a + (-b)) 1 Note that (- b) is 1’s comp CarryOut Add a 1 into CarryIn 0 to get 2’s comp 22
ALU with Zero Detection — for comparing a and b Control Lines Function 000 and 001 or 010 add 110 sub 23
Overflow Result too large for finite computer word: – e.g., adding two n-bit numbers does not yield an n-bit number 0111 note that overflow term is somewhat misleading , + 0001 1000 it does not mean a carry “overflowed” 24
Detecting Overflow No overflow when adding a positive and a negative number No overflow when signs are the same for subtraction Overflow occurs when the value affects the sign: – overflow when adding two positives yields a negative – or, adding two negatives gives a positive – or, subtract a negative from a positive and get a negative – or, subtract a positive from a negative and get a positive Consider the operations A + B, and A – B – Can overflow occur if B is 0 ? – Can overflow occur if A is 0 ? Yes 25
Example Overflow Logic A N B N S N ' A N ' B N ' S N AND AND OR Overflow if ‘1’ How is this derived? – Homework! 26
Effects of Overflow An exception (interrupt) occurs – Control jumps to predefined address for exception – Interrupted address is saved for possible resumption Details based on software system / language – example: flight control vs. homework assignment Don't always want to detect overflow – MIPS instructions: addu, addiu, subu – More later 27
Common Symbol for ALU ALU operation a Zero ALU Result Overflow b CarryOut 28
Recall Full Adder AB’ + A’B ABC in + AB’ C in ’ + A’BC in ’ + A’B’ C in A B C in ( A ⊕ B)C in AB ( A ⊕ B)C in + AB Graph from: Logic and Computer Design 29 Fundamentals, Mano & Kime, Prentice Hall
Full Adder - Half Adders 2 delays 3 delays 4 delays From Z to C is 2 delays for each subsequent stage or 2N + 2 Graphics from: Logic and Computer Design 30 Fundamentals, Mano & Kime, Prentice Hall
4 Bit Ripple Carry Adder 2 2 2 4 2n+2 gate delays (10) for 2’s complement 31
Carry Lookahead Equations Let g i = a i b i generating carry p i = a i + b i propagating carry c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 1 = g 0 +p 0 c 0 c 2 = b 1 c 1 + a 1 c 1 + a 1 b 1 c 2 = g 1 +(p 1 g 0 )+(p 1 p 0 c 0 ) c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 c 3 = g 2 +p 2 g 1 +(p 2 p 1 g 0 )+(p 2 p 1 p 0 c 0 ) c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3 c 4 = g 3 +p 3 g 2 +p 3 p 2 g 1 +(p 3 p 2 p 1 g 0 )+(p 3 p 2 p 1 p 0 c 0 ) P 0-3 G 0-3 32
Should be an OR gate.. What happened? Reduces delay to 6 gate delays (from input to S) 4 gate delays from input to C Carry Lookahead Adder 33
Carry Lookahead – Second Level CarryIn a0 CarryIn b0 Result0--3 a1 b1 ALU0 a2 pi P0 b2 gi G0 a3 b3 Carry-lookahead unit C1 ci + 1 a4 CarryIn b4 Result4--7 a5 b5 ALU1 a6 pi + 1 P1 b6 gi + 1 G1 a7 b7 C2 ci + 2 a8 CarryIn b8 Result8--11 a9 b9 ALU2 a10 pi + 2 P2 b10 G2 gi + 2 a11 b11 C3 ci + 3 a12 CarryIn b12 Result12--15 a13 b13 ALU3 a14 pi + 3 P3 b14 gi + 3 G3 a15 C4 ci + 4 b15 34 CarryOut
Carry Propagation 2’s complement best 1’s complement twice as long Significant delay reduction using Carry Look Ahead concept 35
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