Josef Ressel Center for Verification of Embedded Computing Systems - PowerPoint PPT Presentation

Josef Ressel Center for Verification of Embedded Computing Systems A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs IEEE I2MTC 2015 May 11-14, 2015 | Pisa, Italy Dominik Widhalm 1 , Stefan Tauner 1 , Martin Horauer 1 Achim Schumacher 2 , Alexander Haggenmiller 2 1 UAS Technikum Wien, 2 Infineon Technologies Austria AG

MC ECU A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 1/17

MC ECU Agenda 1 Verification Efforts for Modern Automotive Microcontrollers 2 Bridging the Verification Gap(s) A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 1/17

AURIX TC29xx Data Flash Progr. Progr. RAM BROM FPU Flash Flash Key Flash PMI DMI TriCore 1.6P LMU Program Memory Unit (PMU) Shared Ressource EBU Interconnect (SRI) Checker Core Checker Core Bridge HSSL DMA FPU FPU OCDS PMI DMI PMI DMI TriCore TriCore 1.6P 1.6P System Peripheral Bus (SPB) Ports HSM Generic Timer GPT12x CCU6x STM SCU BCU IOM PLL Module (GTM) DS-ADCx VADCx MultiCAN+ Embedded Voltage Ethernet FlexRay ASCLINx Regulator (EVR) QSPIx MSCx SENT PSI5 FCE I²C 5V or 3.3V Single Supply A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 2/17

AURIX TC29xx — ADCs Data Flash Service Req. Digital Input Auxiliary Filter Progr. Progr. RAM BROM FPU and Comparator Flash Flash Input Result Analog Key Flash PMI DMI Analog Select Input(s) TriCore Adjust Service Req. DS 1.6P Main Filter Chain LMU 10 DS Modulator Program Memory Unit (PMU) Result ADCs . . . Shared Ressource EBU Interconnect (SRI) Checker Core Checker Core Bridge HSSL DMA FPU FPU OCDS PMI DMI PMI DMI TriCore TriCore Result Glob. Result 1.6P 1.6P Handling Register . . . Request System Peripheral Bus (SPB) Ports Arbiter Sources HSM Generic Timer GPT12x CCU6x Clock STM SCU BCU IOM PLL Module Converter Control (GTM) . . . DS-ADCx S&H Unit Triggers, Service Requests VADCx . . . . . . . . . MultiCAN+ Embedded Voltage Ethernet FlexRay ASCLINx Regulator (EVR) QSPIx MSCx SENT PSI5 FCE 11 SAR-ADCs (8 channels each) I²C 5V or 3.3V Single Supply A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 3/17

Design Flow Speci fi cation High-Level Design Low-Level Design RTL Coding (IP & System Level) Functional Veri fi cation Gate-Level Simulation Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Veri fi cation Firmware, Drivers, System Software Design and Validation A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 4/17

Design Flow Speci fi cation High-Level Design Low-Level Design RTL Coding (IP & System Level) Functional Veri fi cation Gate-Level Simulation Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Veri fi cation Firmware, Drivers, System Software Design and Validation A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 4/17

AURIX Pre-Silicon Verification Activities • Simulation → AGENtiX & Cadence Tools (Incisive, Specman etc.) • Emulation → AGENtiX • Static Analysis → Cadence & Infineon Tools (e.g., GateCheck) • Equivalence Checks → Cadence Encounter (Conformal EC) & Infineon Tools (e.g., GateComp) • Assertion-based Verification (ABV) → Cadence & Infineon Tools (e.g., GateProp) A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 5/17

AGENtiX — A SystemC Simulation Environment TOP Basic3SC Testbench DUT XTALF Clock Generator CPUF CPUN PORST Pulse L M Generator CPU/ N O TC/ Proxy SC_THREAD3run3Iv SC_THREAD3run3Iv P/ PF 3333dacMsetI/l3X///v; 3333dacMsetI/l3X///v; TCF 3333spi/MsendDataI/xFNv; 3333spi/MsendDataI/xFNv; Proxy 3333p//_/3=3SC_LOGIC_F; 3333p//_/3=3SC_LOGIC_F; 3333spi/MreceiveDataIbv; 3333spi/MreceiveDataIbv; 3333p//_/3=3SC_LOGIC_/; 3333p//_/3=3SC_LOGIC_/; JTAG3If TCN Proxy JTAG Host TestbenchXxx SC_THREAD3Isv IClusterv Clock MON MON BFM BFM 3333eMgM3runIv Generator 3333for3Inbox Specman Bridge Peripheral3specific Message MonitorsoBFMs Router A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 6/17

Post-Silicon Verification Activities Speci fi cation High-Level Design Low-Level Design RTL Coding (IP & System Level) Functional Veri fi cation Gate-Level Simulation Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Veri fi cation Firmware, Drivers, System Software Design and Validation A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 7/17

AURIX Post-Silicon Verification Activities • SoC Testing → Clock distribution, reset handling, code execution, module interaction etc. • Mixed-signal testing → Module interaction, crosstalk etc. • Power tests → Power modes, envelope etc. • EMC conformance & ESD Tests • Robustness/stress tests Lots of different tools and departments involved, e.g.: • PCB support and robustness testing in Bangalore, India • Flash tests in Munich, Germany • CPU verification in Bristol, GB • Two departments in Villach, Austria, with over 100 employees for ADC, power, PLL etc. (numbers include non-verification-specific positions) A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 8/17

ADC Post-Silicon Verification • Laboratory instruments & DUT controlled via VBA scripts in Excel • Relies on various DLLs for actual communication A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 9/17

Classic Design Flow Speci fi cation High-Level Design Low-Level Design RTL Coding (IP & System Level) Functional Veri fi cation Gate-Level Simulation Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Veri fi cation Firmware, Drivers, System Software Design and Validation A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 10/17

Actual Design Flow Speci fi cation High-Level Design Low-Level Design RTL Coding (IP & System Level) Functional Veri fi cation Gate-Level Simulation Logic Synthesis Place & Route Silicon Fabrication Post-Silicon Veri fi cation Firmware, Drivers, System Software Design and Validation Manufacturer Customer Tier 1 Suppliers A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 10/17

Verification Gaps in the Design Flow Speci fi cation High-Level Design Low-Level Design RTL Coding (IP & System Level) Functional Veri fi cation Gate-Level Simulation Logic Synthesis Cadence Tools / AGENtiX Place & Route Silicon Fabrication Excel Sheets / Post-Silicon Veri fi cation Matlab etc. Firmware, Drivers, System Software Design and Validation Manufacturer Customer User-mode Tier 1 Suppliers test cases A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 11/17

Verification Gaps in the Design Flow Speci fi cation High-Level Design Low-Level Design RTL Coding (IP & System Level) Functional Veri fi cation Gate-Level Simulation Logic Synthesis Cadence Tools / AGENtiX Place & Route Silicon Fabrication Excel Sheets / Post-Silicon Veri fi cation Matlab etc. Firmware, Drivers, System Software Design and Validation Manufacturer Customer User-mode Tier 1 Suppliers test cases A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 11/17

Overview of Novel Bridging Approach User Input Platform-Independent Human-readable Con fi guration T est Case Environment T est Case Information Elements AGENtiX Environment- Legacy Execution Converter speci fi c Converter Module Module Information Module Machine-readable Simulation Executable Physical T est Case Format Environment Image Environment (AGENtiX) Legacy Exchange Format Pre-Silicon Veri fi cation Post-Silicon Veri fi cation Legacy Environment A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 12/17

Overview of Novel Bridging Approach User Input Platform-Independent Human-readable Con fi guration T est Case Environment T est Case Information Elements AGENtiX Environment- Legacy Execution Converter speci fi c Converter Module Module Information Module Machine-readable Simulation Executable Physical T est Case Format Environment Image Environment (AGENtiX) Legacy Exchange Format Pre-Silicon Veri fi cation Post-Silicon Veri fi cation Legacy Environment A Common Platform for Bridging Pre- and Post-Silicon Verification in Mixed-Signal Designs 12/17