Introduction to hardware design of block ciphers Francesco Regazzoni Francesco Regazzoni 20 October 2015, Chia, Italy P. 1
Contents 1 Hardware Design 2 ASIC 3 Reconfigurable Devices Francesco Regazzoni 20 October 2015, Chia, Italy P. 2
Top-Down Approach From an high level specification (usually abstract) to detailed design by decomposition and successive refinement Answers to the question: “What do we build?” Handles the complexity Francesco Regazzoni 20 October 2015, Chia, Italy P. 3
Bottom-Up Approach From detailed primitive blocks to a larger and more complex functional block by combining primitives blocks Answers to the question: “How do we build it?” Focuses on the details Design usually proceed from both directions simultaneously Francesco Regazzoni 20 October 2015, Chia, Italy P. 4
Why Electronic Design Automation? Handle the complexity Design optimization Time to market Francesco Regazzoni 20 October 2015, Chia, Italy P. 5
Design Goals Speed Area Occupation Power Consumption Time to market Cost Francesco Regazzoni 20 October 2015, Chia, Italy P. 6
Speed Latency: time required to perform an action, measured in units of time (nanoseconds, clock periods, ...). Throughput: the number of such actions executed per unit of time, measured in units of what is being produced. Critical path: the path which creates longest delay 1 Clock ≈ criticalpath Francesco Regazzoni 20 October 2015, Chia, Italy P. 7
Area Occupation Amount of silicon area occupied by the whole design Francesco Regazzoni 20 October 2015, Chia, Italy P. 8
Power Consumption Power = Current × Voltage, measured in Watt Francesco Regazzoni 20 October 2015, Chia, Italy P. 9
Power vs Energy Power = Current × Voltage, measured in Watt Energy = Power × Execution time, measured in Joule Francesco Regazzoni 20 October 2015, Chia, Italy P. 10
Time to Market and Cost Consumer electronic.... Non Recurring Engineering Costs Francesco Regazzoni 20 October 2015, Chia, Italy P. 11
Security? Francesco Regazzoni 20 October 2015, Chia, Italy P. 12
Contents 1 Hardware Design 2 ASIC 3 Reconfigurable Devices Francesco Regazzoni 20 October 2015, Chia, Italy P. 13
Simplified Hardware Design Flow (ASIC) Algorithm Design C, Matlab, VHDL Francesco Regazzoni 20 October 2015, Chia, Italy P. 14
Simplified Hardware Design Flow (ASIC) Algorithm Design C, Matlab, VHDL RTL (Architecture) Design Synthesizable HDL Francesco Regazzoni 20 October 2015, Chia, Italy P. 14
Simplified Hardware Design Flow (ASIC) Algorithm Design C, Matlab, VHDL RTL (Architecture) Design Synthesizable HDL Gate x x XOR y y Francesco Regazzoni 20 October 2015, Chia, Italy P. 14
Simplified Hardware Design Flow (ASIC) Algorithm Design C, Matlab, VHDL RTL (Architecture) Design Synthesizable HDL Gate x x XOR y y Layout Francesco Regazzoni 20 October 2015, Chia, Italy P. 14
Standard Cell Library Library of Basic Gates (AND2x1, AND3x1, OR2X1...) Information about Logic function, power, area, timing Vertical and Horizontal Grid are defined All cells must have the same height Francesco Regazzoni 20 October 2015, Chia, Italy P. 15
Synthesis RTL (Architecture) Design Synthesizable HDL Logic Synthesis Gate Level x x XOR y y Francesco Regazzoni 20 October 2015, Chia, Italy P. 16
Definitions Logic Synthesis is the manipulation of logic specifications to create logic models as an interconnection of logic primitives Logic Synthesis determines the gate level structure of a circuit From G. De Micheli, Synthesis and Optimization of Digital Circuits , McGraw-Hill Higher Education, 1994. Francesco Regazzoni 20 October 2015, Chia, Italy P. 17
Logic Synthesis Input and Output INPUT : HDL Description Technological Library (function, area, timing, power, environmental constraints) Synthetic Library (multipliers...) Constraints OUTPUT : Gate Level Netlist Estimation of area, timing, power (!) Timing constraints Francesco Regazzoni 20 October 2015, Chia, Italy P. 18
Typical Logic Synthesis Steps one State Minimization two State Encoding three Combinatorial Logic Minimization four Technology Mapping Francesco Regazzoni 20 October 2015, Chia, Italy P. 19
Place and Route Gate x x XOR y y Place and Route Layout Francesco Regazzoni 20 October 2015, Chia, Italy P. 20
Place and Route Input and Output INPUT : Gate level description of the circuit Physical view of the library (pin placement, ...) Constraints from synthesis OUTPUT : Gate Level Netlist Position and interconnection of the gates Estimation of area, timing, power (!) Francesco Regazzoni 20 October 2015, Chia, Italy P. 21
This is not yet the end! PADs Design Rule Checks Layout vs Schematic Check Tape out Francesco Regazzoni 20 October 2015, Chia, Italy P. 22
Contents 1 Hardware Design 2 ASIC 3 Reconfigurable Devices Francesco Regazzoni 20 October 2015, Chia, Italy P. 23
Reconfigurable Devices Field Programmable Gate Arrays (FPGAs) Reconfigurable hardware devices Trade offs between ASIC and microprocessors Current progresses allow to store a complete SoC on FPGA Francesco Regazzoni 20 October 2015, Chia, Italy P. 24
Advantages of FPGA Reduced non recurring engineering costs Reduced time to market Easier access to newer technologies Francesco Regazzoni 20 October 2015, Chia, Italy P. 25
High Level View Configurable blocks (look-up-tables) Configurable routing matrix Input/Output blocks Memory configuration Advanced processing elements (DSP , whole processors) Francesco Regazzoni 20 October 2015, Chia, Italy P. 26
Simplified Hardware Design Flow (FPGAs) HDL Francesco Regazzoni 20 October 2015, Chia, Italy P. 27
Simplified Hardware Design Flow (FPGAs) HDL Synthesis Francesco Regazzoni 20 October 2015, Chia, Italy P. 27
Simplified Hardware Design Flow (FPGAs) HDL Synthesis Place and route Francesco Regazzoni 20 October 2015, Chia, Italy P. 27
Simplified Hardware Design Flow (FPGAs) HDL Synthesis Place and route Generate the bit stream Francesco Regazzoni 20 October 2015, Chia, Italy P. 27
Simplified Hardware Design Flow (FPGAs) HDL Synthesis Place and route Generate the bit stream Burn the FPGA Francesco Regazzoni 20 October 2015, Chia, Italy P. 27
Hardware Design Final Remarks Don’t compare apple with oranges! Francesco Regazzoni 20 October 2015, Chia, Italy P. 28
Questions? Thank you for your attention! mail: regazzoni@alari.ch Francesco Regazzoni 20 October 2015, Chia, Italy P. 29
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