Implementation of Advanced Solar-Cell Analysis at Cell Test Ronald - PowerPoint PPT Presentation

Implementation of Advanced Solar-Cell Analysis at Cell Test Ronald A. Sinton, Adrienne L. Blum Wes Dobson, Harrison Wilterdink, Justin H. Dinger, Cassidy Sainsbury Sinton Instruments, Boulder, CO, 80301, USA

A vision for end-to-end metrology for electronic quality (1999 NREL Silicon Workshop)

A vision for end-to-end metrology for electronic quality (2016 NREL Silicon Workshop) Step Metric Fundamental Analysis Impact Analysis Feedstock τ vs. Δn τ vs. Δn Implied IV curve Crystal τ vs. Δn, Ω -cm, trapping τ vs. Δn Implied IV curve Wafer τ vs. Δn, Ω -cm, trapping τ vs. Δn Sorting Dopant diffusion τ vs. Δn, Ω -cm, trapping τ vs. Δn Implied IV curve Passivation τ vs. Δn, Ω -cm, trapping τ vs. Δn Implied IV curve Cell I, V, R s , R sh , τ vs. Δn , N A τ vs. Δn Real/pseudo-IV curve Module I, V, R s , R sh , τ vs. Δn , N A τ vs. Δn Real/pseudo-IV curve System I, V, R s , R sh , τ vs. Δn , N A τ vs. Δn Real/pseudo-IV curve

Feedstock Qualification (Lifetime Test)

Feedstock Qualification (Lifetime Test) 7.38 ms

Suns-V oc Curves at the Array Level (3.6 KW)

A vision for end-to-end metrology for electronic quality Step Metric Fundamental Analysis Impact Analysis Feedstock τ vs. Δn τ vs. Δn Implied IV curve Crystal τ vs. Δn, Ω -cm, trapping τ vs. Δn Implied IV curve Wafer τ vs. Δn, Ω -cm, trapping τ vs. Δn Sorting Dopant diffusion τ vs. Δn, Ω -cm, trapping τ vs. Δn Implied IV curve Passivation τ vs. Δn, Ω -cm, trapping τ vs. Δn Implied IV curve Cell I, V, R s , R sh , τ vs. Δn , N A τ vs. Δn Real/pseudo-IV curve Module I, V, R s , R sh , τ vs. Δn , N A τ vs. Δn Real/pseudo-IV curve System I, V, R s , R sh , τ vs. Δn , N A τ vs. Δn Real/pseudo-IV curve

Cell Test is Unique: 100% Testing of Wafers We need to take maximum advantage of this opportunity! Device physics at cell test: • Lifetime vs. injection level • bulk lifetime and emitter saturation current densities • Relevant measurement of series resistance (Suns-V oc curve) • Time response of high-efficiency cells (Capacitance) • Examples: • n-type high-efficiency solar cell • A study of p-type solar cells spanning low to high efficiency • Power loss analysis for record-efficiency cell

R&D and Production Cell Testing • Laboratory cell tester • MultiFlash technology • Measures full IV curve with conventional parameters (Eff, J sc , V oc , V mp , J mp , FF) • Measures Suns-V oc (pseudo parameters, lifetime vs. injection level, J 0 , BRR, lifetime at V mp , dark R sh , SUBSTRATE DOPING) • Production cell tester • Production cell tester (250 MW installed in production to date) • All the same parameters • New SingleFlash technology enables high-speed testing • Potential for 4800 tests per hour • ~ 200ms cell test time of stationary cell

Methodology: Outline Parameter Method IV parameters MultiFlash or SingleFlash technology; filtered Xenon light Substrate doping Time-dependent continuity equation Lifetime vs. excess carrier density Time-dependent Suns-V oc data using doping result R s Evaluation of IV and Suns-V oc curves at J mp R sh Ohm-meter in dark at 0 Volts Voltage (Strategic, 6 points) 8 Channel simultaneous data acquisition Current same Intensity same (using silicon reference cell) Temperature RTD Capacitance effects Constant charge method ( EUPVSEC Dresden, 2006)

Lifetime data: Everyone does this with test wafers and a lifetime tester V mp

IV curves: BSF, PERC, n-type, Auger limit

But it is the same thing! Lifetime data and IV data ∆𝑜 𝑙 , ∆𝑜 𝑙+1 , ∆𝑜 𝑙+2 … Calculate Recombination: Calculate Voltage: 𝑊 + 𝐾𝑆 𝑡 = 𝑙𝑈 𝑂 𝐵 + ∆𝑞 ∆𝑜 𝐾 = 𝑄ℎ𝑝𝑢𝑝𝑕𝑓𝑜𝑓𝑠𝑏𝑢𝑗𝑝𝑜 𝑟 ln −𝑆𝑓𝑑𝑝𝑛𝑐𝑗𝑜𝑏𝑢𝑗𝑝𝑜 − 𝑊 𝑜 𝑗2 𝑆 𝑡ℎ (𝐾 𝑙 , 𝑊 𝑙 ), (𝐾 𝑙+1 , 𝑊 𝑙+1 ), … Including series resistance and shunt

IV in Terms of Emitters and Bulk Lifetime 𝑊 = 𝑙𝑈 𝑟 ln (𝑂 𝐵 + ∆𝑞)(∆𝑜) − 𝐾𝑆 𝑡 𝑜 𝑗2 𝐷𝑣𝑠𝑠𝑓𝑜𝑢 = 𝑄ℎ𝑝𝑢𝑝𝑕𝑓𝑜𝑓𝑠𝑏𝑢𝑗𝑝𝑜 − ∆𝑜𝑟𝑋 𝑂 𝐵 + ∆𝑞 ∆𝑜 − 𝑊 + 𝐾 0𝑔𝑠𝑝𝑜𝑢 + 𝐾 0𝑐𝑏𝑑𝑙 𝑜 𝑗2 𝜐 𝑐𝑣𝑚𝑙 𝑆 𝑡ℎ [Recombination] “Thin - base limit”

IV in Terms of Emitters and Bulk Lifetime 𝑊 = 𝑙𝑈 𝑟 ln (𝑂 𝐵 + ∆𝑞)(∆𝑜) − 𝐾𝑆 𝑡 𝑜 𝑗2 𝐷𝑣𝑠𝑠𝑓𝑜𝑢 = 𝑄ℎ𝑝𝑢𝑝𝑕𝑓𝑜𝑓𝑠𝑏𝑢𝑗𝑝𝑜 − ∆𝑜𝑟𝑋 𝑂 𝐵 + ∆𝑞 ∆𝑜 − 𝑊 + 𝐾 0𝑔𝑠𝑝𝑜𝑢 + 𝐾 0𝑐𝑏𝑑𝑙 𝑜 𝑗2 𝜐 𝑐𝑣𝑚𝑙 𝑆 𝑡ℎ

R s Measurement Using Suns-V oc Curve R sh = Δ V/ Δ J R s = Δ V/J mp R s from Suns-V oc does NOT depend on quality of fit to a model (no 1- or 2-diode equations or such nonsense)

Biggest Challenge with High-Efficiency n-type Time response of high-efficiency cells (capacitance)

Ramp-rate Artifacts (PC1D simulations) Modeled Si cell (V oc = 720 mV, thickness = 200 µm) IV curves at different ramp rates 0.045 0.040 0.035 Current Density (A/cm 2 ) Voltage Ramp Rates Steady State 0.030 0.8 100 ms 2 ms 100 ms 0.7 50 ms 0.025 0.6 Voltage/Cell 0.5 20 ms 0.020 0.4 10 ms (industry std) 0.3 0.015 0.2 5 ms 0.1 2 ms 0.010 0 0 20 40 60 80 100 0.005 Time (ms) 0.000 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Voltage (V)

High-Efficiency n-type Cells: 200X Higher Capacitance! SunPower, Sanyo 2016 PERC Cell (3 Ω -cm) Standard Screen Print (1 Ω -cm)

Eliminating errors due to slow time response during flash testing ∆𝑜 𝑙 , ∆𝑜 𝑙+1 , ∆𝑜 𝑙+2 … Calculate Recombination: Calculate Voltage: 𝑊 + 𝐾𝑆 𝑡 = 𝑙𝑈 𝑂 𝐵 + ∆𝑞 ∆𝑜 𝐾 = 𝑄ℎ𝑝𝑢𝑝𝑕𝑓𝑜𝑓𝑠𝑏𝑢𝑗𝑝𝑜 𝑟 ln −𝑆𝑓𝑑𝑝𝑛𝑐𝑗𝑜𝑏𝑢𝑗𝑝𝑜 − 𝑊 𝑜 𝑗2 𝑆 𝑡ℎ (𝐾 𝑙 , 𝑊 𝑙 ), (𝐾 𝑙+1 , 𝑊 𝑙+1 ), … Sol olution: Test under constant ch charge condit itions: Measure V and J, while holding (V + J × R s ) constant using a feedback circuit. 10 years of industrial production and R&D experience with this technique. R. A. Sinton, 21st EU PVSEC, (2006); pp. 634-638 ; US patents 7696461 B2 2010, 7309850B2 2007

Eliminating errors due to slow time response during flash testing • SintonDresden2006.pdf Sol olution: Test under constant ch charge condit itions: Measure V and J, while holding (V + J × R s ) constant using a feedback circuit. 10 years of industrial production and R&D experience with this technique. R. A. Sinton, 21st EU PVSEC, (2006); pp. 634-638 ; US patents 7696461 B2 2010, 7309850B2 2007

Example: IV test of a high-efficiency n-type cell High-Efficiency n-type

IV-test example: N-type high efficiency

IV-test example: N-type high efficiency 2 W Jof+ Job = slope*qn i Bulk lifetime @ -N D

IV-test Example: n-type High Efficiency

Example: IV test of a PERC cell PERC cell

Example: IV test of a PERC cell

IV-test example: PERC cells

Lifetime and Substrate Doping Measurements of Solar Cells and Application to In-Line Process Control Adrienne L. Blum Wes Dobson, Harrison Wilterdink, Justin H. Dinger, Ronald A. Sinton Sinton Instruments, Boulder, CO, 80301, USA IEEE PVSC, Portland, Oregon, 2016

Measurement Samples: P-type Study • P-type cells processed with varying techniques: • Multi-crystalline Al BSF cells • High Performance Multi-crystalline Al BSF cells • Multi crystalline PERC cells • Monocrystalline PERC cells • Monocrystalline PERC cells A. Blum et al. IEEE PVSC, Portland, Oregon, 2016

Doping Measurement: An Opportunity Substrate doping and t vs. D n at the cell level • • Substrate doping • Wafer position in ingot or brick  prediction of [O]/other impurities  potential prediction of LID behavior • Information relevant to lateral series resistance in PERC cells • Gives final substrate doping, including changes from high temp steps • Effective lifetime • Surface passivation quality • Substrate quality • Contamination during high-temperature processing A. Blum et al. IEEE PVSC, Portland, Oregon, 2016

Measurement Parameters • Analyze pV mp and efficiency dependence on substrate doping (N A ) and effective lifetime ( τ eff ) • pV mp is used because the five groups of cells come from different processing techniques, allows for a comparison independent of R s • pV mp : 515-584mV • Efficiency: 15.8-21% • τ eff : 5-100 μ s • N A : 5×10 15 -3×10 16 cm -3 A. Blum et al. IEEE PVSC, Portland, Oregon, 2016

pV mp and Efficiency Correlate to τ ×N A • Five different cell processing techniques all follow the same trend 0.59 mc-Si Al BSF mc-Si (high 0.58 performance)Al BSF 0.57 mc-Si PERC Mono PERC 0.56 pVmp (V) Mono PERC 0.55 0.54 0.53 0.52 0.51 16 17 18 10 10 10 t x N A (  s/cm 3 ) 𝐾 𝑡𝑑 − 𝐾 𝑂 𝐵 + ∆𝑜)𝜐 𝑓𝑔𝑔 𝑊 + 𝑆 𝑡 𝐾 = 𝑙𝑈 𝑟 𝑚𝑜 𝑟𝑋𝑜 𝑗2 A. Blum et al. IEEE PVSC, Portland, Oregon, 2016