Implementation of a noise subtraction algorithm using Verilog HDL - PowerPoint PPT Presentation

Implementation of a noise subtraction algorithm using Verilog HDL University of Massachusetts, Amherst Department of Electrical & Computer Engineering, Course 559/659 by Perry Levy, Aseem Pangotra, Stephan Stiglmayr and Thomas Kunkel Team Leader: Prof. Maciej Ciesielski

Noise-subtracting algorithm � Time to frequency transformation Algorithm Algorithm � Subtraction of magnitudes Modules � Distortion correction In- / Output � Frequency to time transformation FFT Subtraction

Noise-subtracting algorithm Algorithm Modules Modules In- / Output FFT Subtraction

Noise-subtracting algorithm Algorithm � Serial data Modules � Shifts of 16bits In- / Output In- / Output � Storing in 1032 x 32bit memory FFT � Flushing memory to FFT after Subtraction receiving of 256 pairs of data

Noise-subtracting algorithm State machine Algorithm Flushing storing data in Reset 256 pairs memory memory Modules Buffer emptied In- / Output In- / Output Emptying Buffering data Mem buffer FFT flushed Subtraction

Noise-subtracting algorithm Block Diagram Address Address Data WR RD Algorithm generator SCLK Valid Flushing Real part Serial LRCLK Output Modules shifter Imaginary 1024 x 32bit Reset Data Data Buffer RAM Done Enable In- / Output In- / Output Hold FFT 16bit counter Finite state machine Subtraction

Noise-subtracting algorithm � Parallel input and output of variables Algorithm � 16Bit address, 8Bit data (compatible to microcontroller) Modules � Preset values when resetting In- / Output In- / Output FFT Subtraction

Noise-subtracting algorithm � Implementation of Radix 2 algorithm Algorithm � Window length 1024 Modules � 16Bit fixed point arithmetics In- / Output � 2 FFTs at the same time by using real and imaginary signal FFT FFT � Reconstruction afterwards needed Subtraction

Noise-subtracting algorithm � Butterfly structure as fundamental cell Algorithm k B ( k ) C ( k )= A ( k )� W k B ( k ) D ( k )= A ( K )� W Modules In- / Output A C + FFT FFT + B D x - Subtraction W k

Noise-subtracting algorithm Signal-flow Graph for 8 point FFT f(0) F(0) Algorithm F(1) -1 W 0 F(2) -1 Modules W 2 F(3) -1 -1 In- / Output W 0 F(4) -1 FFT FFT W 1 F(5) -1 -1 W 0 W 2 Subtraction F(6) -1 -1 W 2 W 3 f(7) F(7) -1 -1

Noise-subtracting algorithm � Sequential implementation Algorithm � 1Bit shiftdown after each step to prevent overflow Modules � RAM 1024 x 32Bit In- / Output � Controller (Finite state machine) FFT FFT � Address generator Subtraction � Coefficient ROM

Noise-subtracting algorithm Block Diagram output_ready input_ready Algorithm bus_select Controller Modules write_en RAM read_en 32 Data In 32 input_mode e ram_addr1 fft_mode fft_done io_done d In- / Output Data o ram_addr2 m Bus _ o i Butterfly 1 Processor 32 FFT 32 FFT Data Out 0 Address Generator 10 twiddle Subtraction 10 Coeff. ROM rom_addr FFT PROCESSOR

Noise-subtracting algorithm Delay estimation Algorithm • Input: 512 • FFT processing: 2*512*10 Modules • output: 512 In- / Output Sum 11264 clock cycles FFT FFT Subtraction

Noise-subtracting algorithm Simulations Verilog output 500 400 Algorithm abs(X1) 300 200 Modules 100 0 0 2000 4000 6000 8000 10000 12000 In- / Output Matlab FFT (32 bit float) 500 400 FFT FFT abs(X2) 300 200 Subtraction 100 0 0 2000 4000 6000 8000 10000 12000 frequency

Noise-subtracting algorithm Spectra reconstruction 1 2 ( F ( k )� F ( n � k )) Algorithm Re Im 1 2 ( F ( k )� F ( n � k )) Modules Re 1 Im 2 ( F ( k )� F ( n � k )) In- / Output Re Im 1 FFT FFT 2 ( F ( k )� F ( n � k )) Subtraction

Noise-subtracting algorithm Error compared to 32bit floating point Absolute Error 0.4 Algorithm 0.35 0.3 Modules 0.25 In- / Output 0.2 0.15 FFT FFT 0.1 Subtraction 0.05 0 0 2000 4000 6000 8000 10000 12000

Noise-subtracting algorithm Error compared to 32bit floating point = π ⋅ ⋅ + π ⋅ ⋅ x cos( 2 1700 t ) j sin( 2 500 t ) Time window weighted with hanning function (dumped from FFT memory) 4 1 x 10 Algorithm 0.5 Modules 0 -0.5 In- / Output -1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 4 1 x 10 FFT FFT 0.5 Subtraction 0 -0.5 -1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

Noise-subtracting algorithm Error compared to 32bit floating point 5 Recontructed Spectra 4 x 10 3 Algorithm Matlab Verilog 2 1 Modules 0 0 1000 2000 3000 4000 5000 6000 5 In- / Output 4 x 10 3 FFT FFT 2 1 Subtraction 0 0 1000 2000 3000 4000 5000 6000 frequency [Hz] (absolute values plotted)

Noise-subtracting algorithm Block diagram Algorithm Beta 16 Modules 1 if x>y, else 0 x a Comp In- / Output sel b FFT Sub Subtraction Subtraction Alpha

Noise-subtracting algorithm • Inputs: two, 16 unsigned bits each ( A and B) Algorithm • Multiplication: Alpha and Beta terms • Subtraction: ((original A)-(Alpha*B)) Modules • Comparators: (A > B) out =1, else out =0 In- / Output • Multiplexer: (Inputs: Select, A*Beta, subtractor output) FFT Select = 1, final_out = x Subtraction Subtraction Select = 0, final_out = y