Impact of Process and Temperature Variations on Network-on-Chip - PowerPoint PPT Presentation

Impact of Process and Temperature Variations on Network-on-Chip Design Exploration Bin Li, Li-Shiuan Peh, Priyadarsan Patra* *Intel Corporation Princeton University {binl, peh}@princeton.edu priyadarsan.patra@intel.com April 9,2008

Process and Temperature Variations � Process variation has higher impact on sub-100 nm CMOS � Transistor dimension variation : Sub-wavelength lithography � Transistor characteristic variation: Dopant density fluctuation etc � Temperature variations: caused by workload variation Chip thermal profile Power 4 Server Chip floorplan [IBM research, Austin ] 2

Impact on Power Consumption Process Threshold Variation Voltage Variation Leakage Power Temperature Workload Fluctuation Need to consider process variation Need to consider within-die temperature for leakage variation for leakage 3

Current Approaches Need tools that predict the impact of variations on design metrics at early System design stage Microarchitecture Time consuming level: Analytical Small scale modeling [eg. Bowman, JSSE’02] Microarchitecture Circuit level: Expensive to implement Eg: Adaptive Body Often too late for changes Biasing, Adaptive Circuit Voltage Scaling [Tschanz, JSSC’02] 4

Current Approaches � Workload variation not considered [eg:Humenay, ASGI’06] System � Limitation in Develop tools that predict System level: architecture variety, the impact of variations Simulation with Microarchitecture small scale [eg. on power at early design statistical model Chandra, ISLPED’06] stage � Most work focuses on Circuit performance, not power 5

Network-on-Chip (NoC) for CMP CMP Core Core Core Core Core Core NoC R R R power is Core Core Core Core Core Core large R R R System Core Core Core Core Core Core R R R Develop tools that predict Micro-architecture the impact of variations on � MIT RAW: 36% [J.Kim et al. ISLPED’03] power for NoC � Intel 80-tile TeraFLOPs processor: 39% Circuit [S.Vangal et al., VLSI Circuits’07] 6

Outline � Introduction and Motivation � Methodology and Tool Development � Case Study � Conclusions and Future Work 7

Leverage Polaris Toolchain for Variations Polaris Step 1 Synthetic traffic generation Design-space exploration tool Step 2 LUNA Microarchitecture High-level on-chip network parameters analysis Step 3 ORION power and area models Performance power CMOS area (latency) consumption NoC designs projections V. Soteriou, N. Eisley, H. Wang, B. Li, L.S. Peh, TVLSI’07 8

Polaris: ORION Power Model Network Resource Uniform Utilization from LUNA temperature and no process variation ORION Leakage Power Dynamic Power (Chen, ISLPED’03) Modify ORION to Step 1 Trident Synthetic traffic generation account for process Design-space exploration tool Step 2 LUNA Microarchitecture High-level on-chip network parameters and temperature analysis Step 3 ORION power and variations area models Performance power CMOS area (latency) consumption NoC designs projections 9

New ORION Model (Process and Temperature Aware) D2D Process Network Resource Network Resource Utilization from Utilization from Variation Yellow parts are LUNA LUNA Models the extended parts Utilization Vth Vth we added to ORION ORION ORION Leakage Power Leakage Power Thermal Thermal Dynamic Power Dynamic Power HotLeakage (Chen, ISLPED’03) Profile Profile ISAC P dynamic P leakage Temperature profile Step 1 Trident Synthetic traffic generation Total Power Profile Design-space exploration tool at each process point Step 2 LUNA Power Power Microarchitecture High-level on-chip network parameters analysis Power Profile Profile Step 3 ORION N Set simulation power and number achieved? area models N Performance power Y CMOS area (latency) consumption Power Distributions NoC designs projections 10

Outline � Introduction and Motivation � Methodology and Tool Development � Case Study � Conclusions and Future Work 11

Experimental setup � Technology � 64-node chip � 65nm technology � Supply voltage : 1.2V � Frequency: 3.8GHz � Threshold voltage: � mean=0.25 V � standard deviation= 6% � Die size:14.4mm x 14.4mm x 0.6mm 12

Design Space Explored 2D mesh plain What is the optimal 2D mesh with express cube interval 2,3 on-chip network 2D mesh with hierarchical link interval 2,3,4 architecture for my Topology application? 2D torus plain 2D torus with express cube interval 2, 4 2D torus with hierarchical link interval 2,3,4 Buffer size 4, 8, 16, 32 (64-bit flits) Virtual channels 1, 2, 4, 8 per link Routing Deterministic routing (X-Y) Traffic Long distance, moderately bursty, hot-spot traffic 13

Effects of Process and Temperature Variations on Power Distribution rather than deterministic Average power increases x axis format: topology variant (buffer size, number of virtual channels) Process and temperature variations affect power consumption 14

Effects of Process and Temperature Variations on EDPPF � Average smaller Decision might � Distribution change smaller x axis format: topology variant (buffer size, number of virtual channels) Early design exploration quantify effects of variations EDPPF: Energy-Delay Product Per Flit 15

Other Aspects not Covered � Sensitivity analysis � Only consider temperature variation � Only consider process variation � Mean x standard-deviation metrics 16

Conclusions � Early design stage tool that accounts for process and temperature variations � Process and temperature variation strongly impacts power � Influence design choices � Need to be considered together 17

Future Work � Study how within die process variations affect the network power consumption � Studying process and temperature variation effects on network operating frequency 18

Thank you ! 19