III-V Nanoelectronics for Energy Efficient Information Processing PhD Students: Vinay Saripalli (Intel), Dheeraj Mohata, Bijesh R., Mike Barth, Ashkar Ali Suman Datta Electrical Engineering Materials Research Institute (MRI) March 01, 2012
Energy Efficiency • Near threshold voltage (NTV) computing achieves highest energy efficiency • Can III-V nanoelectronics be employed to enhance transistor characteristics targeted for NTV computing Variable precision floating point unit processor on 32nm CMOS (Source Intel: ISSCC 2012)
Emerging Nano Devices State of the Art CMOS Enhanced CMOS Ge / InGaAs / InSb FINFETs Extended CMOS Beyond CMOS • Leverage emerging Nano devices for advanced, extended and beyond CMOS for energy efficiency
NTV Computing Devices
Antimonide III-V CMOS 2 /Vs] 5 10 Ga 0.6 In 0.4 Sb QW Layers InAs 1-x Sb x QW Layers 2 /Vs] Penn State, NRL (IEDM '10) Stanford, NRL (IEDM '09) x=0.2-0.3 Electron Mobility [cm 3 4 10 Hole Mobility [cm 10 7x 60x 3 Si PMOS 10 2 10 Si NMOS 2 10 1 1 10 10 1E12 1E13 1E12 1E13 2 ] 2 ] Carrier Density [/cm Carrier Density [/cm InAs 1-x Sb x QW electron mobility ~ 13,000 cm 2 /Vs (60x over Si) Ga x In 1-x Sb QW hole mobility ~ 850 cm 2 /Vs (7x over Si) Promising for low power, high-performance III-V CMOS logic
Shared Metamorphic Buffer NMOS PMOS ILD G G S D S D High- κ High- κ InAlSb Barrier InAlSb Barrier Isolation InAsSb QW InGaSb QW InAlSb Barrier InAlSb Barrier Al 0.8 Ga 0.2 Sb buffer (Unified Buffer for NMOS and PMOS) S.I. GaAs Nucleation and Buffer Layer 4 o (100) Offcut Si Substrate Antimonide NMOS and PMOS have similar lattice constants Can be grown on the same buffer Promising for III-V CMOS M. Hudait, S. Datta, R. Chau et al.; US Patent No. 7429747
Outline Device Architecture for Ultra-low V DD Logic • Device Layer Design Work Function Engineered S/D Engineered S/D Work Function Work Function Engineered Metal Metal Gate Metal • Dielectric Integration Strategy High-k gate oxide δ -doped Barrier • Device Transport Characterization High Mobility QW – Long Channel Mobility Bottom Barrier Layer – Short Channel Velocity • Gate Stack Scalability Mismatch Accommodation Layer – Quantum Capacitance Effects • Conclusions Substrate
Quantum Well Device Layer Design GaSb Cap: 2.5 nm QW Device Layers Al 0.8 In 0.2 Sb Barrier: 9 nm 1.5 µm InAs 0.8 Sb 0.2 Channel: 12 nm Al 0.8 Ga .2 Sb Buffer Al 0.8 Ga .2 Sb Buffer 5nm GaAs Substrate InAs 0.8 Sb 0.2 quantum well device layer was modified to incorporate an ultra- thin GaSb cap layer for dielectric integration Any parallel channel in the device ? Device layers grown by Brian R. Bennett, NRL
Quantitative Mobility Spectrum Analysis -2 10 electrons Te δ− doping 300K Al 0.8 Ga 0.2 Sb InAs 0.8 Sb 0.2 2DEG 0.8 holes -4 10 Energy [eV] Conductivity [/ Ω ] -6 0.4 10 GaSb -2 Al 0.8 In 0.2 Sb Al 0.8 In 0.2 Sb 10 2DEG 200K E F E 1 0.0 -4 10 0.3eV E 0 -6 10 -0.4 -2 10 77K 2DEG -4 -0.8 (a) 10 10 20 30 40 -6 10 2 3 4 5 6 Distance [nm] 10 10 10 10 10 2 /Vs] Mobility [cm Higher conductivity peak corresponds to InAs 0.8 Sb 0.2 QW No dominant parasitic channel in the device layers
Hall Mobility and Scattering Analysis 6 10 50 µ % Contribution to 1/ µ T=300K 2 /Vs] Interface Roughness µ µ 40 µ POP Alloy ADP Mobility [cm µ 30 5 10 Remote Ionized Impurity 20 µ Interface Charge µ 10 µ Model 4 10 Experiment 0 Polar Optical Phonon Remote Ionized Impurity Acoustic Phonon Interface Charge Alloy Disorder Interface Roughness 10 100 Temperature [K] Electron mobility of 13,000 cm 2 /Vs at 300K (N s =2.2 x 10 12 /cm 2 ) Coulomb scattering due to interface charge limits transport
Ultra-thin GaSb Cap Layer on InAlSb Barrier Enables High- κ Dielectric Integration 300 nm Surface clean on device Surface clean on device layers layers with InAlSb surface with GaSb cap on InAlSb barrier High Al content barrier oxidizes in air giving rise to surface pitting during surface preparation prior to high- κ deposition GaSb cap layer on InAlSb barrier enables high- κ dielectric integration
n-GaSb MOSCAPs Low Temp Plasma High Temp ALD Enhanced ALD 1.2 75kHz to 2MHz 1.0 -2 ] Gate Capacitance [ µ Fcm 0.8 (Pd/Au) 5nm Al 2 O 3 0.6 n-GaSb 0.4 300K 300K (Te doping) 1.2 N D =1x10 18 /cm 3 1.0 0.8 0.6 0.4 250K 250K -2 -1 0 1 2 -2 -1 0 1 2 Gate Voltage [V] ( ) Plasma Enhanced ALD MOSCAPs show good Fermi level modulation
p-GaSb MOSCAPs Low Temp Plasma High Temp ALD Enhanced ALD 1.2 75kHz to 2MHz 1.0 -2 ] Gate Capacitance [ µ Fcm 0.8 (Pd/Au) 5nm Al 2 O 3 0.6 p-GaSb 0.4 300K 300K (unintentional doping) 1.2 N A =1x10 18 /cm 3 1.0 0.8 0.6 0.4 200K 200K -2 -1 0 1 2 -2 -1 0 1 2 Gate Voltage [V] Plasma Enhanced ALD MOSCAPs show good Fermi level modulation
Interface State Density (D it ) D it extracted from multi-temperature CV/GV analysis of n&p GaSb MOSCAPs Fermi Level movement at Sb QW MOSFET ON-State High Temp ALD high- κ /GaSb interface for E 1.0 C Barrier QW Buffer Oxide Sb QW MOSFET ON-OFF Energy [eV] 0.5 2 /eV] 13 E 10 2 GaSb Sb QW MOSFET E 0.0 F D it [/cm E OFF-State 1 1.5 -0.5 E Barrier QW Buffer Oxide V E Energy [eV] C 1.0 -1.0 Low Temp PEALD 10 20 30 E Distance [nm] 2 GaSb 0.5 12 10 E 0.0 0.2 0.4 0.6 0.8 E 1 0.0 F E-E V [eV] E -0.5 V 10 20 30 Distance [nm] Low D it near E V of GaSb for PEALD Good Sb QW NMOS turn off High D it towards midgap Likely affect drive current
Scaled Gate Stack Low Temperature ALD 3.0 2 ] E C Capacitance [ µ F/cm E V Pd / (5 nm HfO 2 -1 nm Al 2 O 3 ) / p & n-GaSb 75 kHz to 2MHz 2.5 ALD Al 2 O 3 /HfO 2 2 /eV] T OXE =1.4 nm 2.0 13 10 D it [/cm 1.5 PEALD Al 2 O 3 T OXE =3.1 nm 1.0 0.5 12 10 -1 0 1 -1 0 1 0.0 0.2 0.4 0.6 0.8 Gate Voltage [V] E-E V [eV] Al 2 O 3 / HfO 2 bilayer stack enables gate dielectric scaling
Sb NMOSFET Device Fabrication Pd/Pt/Au Pd/Pt/Au As Grown Device Layers Source GaSb : 2.5nm GaSb : 2.5nm Drain Te δ -doping Al 0.8 In 0.2 Sb Barrier : 9nm Te δ -doping Al 0.8 In 0.2 Sb Barrier : 9nm InAs 0.8 Sb 0.2 QW:12nm InAs 0.8 Sb 0.2 QW:12nm Pd/Pt/Au Source-Drain Contacts Al 0.8 Ga 0.2 Sb Buffer : 1.5 μ m and Al 0.8 Ga 0.2 Sb Buffer : 1.5 μ m Device Isolation S.I. GaAs Substrate S.I. GaAs Substrate Gate Stack Processing Final Processed Device (HCl based surface clean) Pd/Au Gate Pd/Pt/Au Pd/Pt/Au Pd/Pt/Au Pd/Pt/Au 1nm Al 2 O 3 /10nm HfO 2 1nm Al 2 O 3 /10nm HfO 2 Source Source GaSb : 1 nm Drain GaSb : 1 nm Drain Te δ -doping Gate Patterning Te δ -doping Al 0.8 In 0.2 Sb Barrier : 9nm Al 0.8 In 0.2 Sb Barrier : 9nm InAs 0.8 Sb 0.2 QW:12nm E-beam Lithography InAs 0.8 Sb 0.2 QW:12nm Al 0.8 Ga 0.2 Sb Buffer : 1.5 μ m Al 0.8 Ga 0.2 Sb Buffer : 1.5 μ m S.I. GaAs Substrate S.I. GaAs Substrate
SEM Micrograph of Sb NMOSFET Pd/Au Gate Pd/Pt/Au Pd/Pt/Au 1nm Al 2 O 3 /10nm HfO 2 Source GaSb : 1 nm Drain Te δ -doping Al 0.8 In 0.2 Sb Barrier : 9nm InAs 0.8 Sb 0.2 QW:12nm Al 0.8 Ga 0.2 Sb Buffer : 1.5 μ m Pd/Au Gate S.I. GaAs Substrate L G = 150 nm Long and short channel Sb NMOSFETs fabricated with composite high- κ gate stack(1 nm Al 2 O 3 / 10 nm HfO 2 on GaSb) Gates defined using electron beam lithography L G = 150 nm–20 µm Devices Fabricated at the Penn State Nanofabrication Facility
Transfer Characteristics of Sb NMOS G m at V DS =0.5 V [ µ S/ µ m] G m at V DS =0.5 V [ µ S/ µ m] G m at V DS =0.5 V [ µ S/ µ m] 600 V DS =0.1V,0.5V 2 V DS =0.1V,0.5V V DS =0.1V,0.5V 10 600 L G =5 µ m L G =150nm L G =450 nm 200 I D & I G [ µ A/ µ m] I D & I G [ µ A/ µ m] I D & I G [ µ A/ µ m] 2 2 10 10 400 1 10 400 1 1 10 10 100 0 10 200 200 0 0 -1 10 10 10 0 0 0 -2 -1 0 -2 -1 0 -2 -1 0 Gate Voltage [V] Gate Voltage [V] Gate Voltage [V] Good I ON -I OFF for long L G devices G m,peak = 400 µS/µm at V DS =0.5V for L G = 450 nm (R ext limits short channel performance) The sub-threshold characteristics degrade as L G is scaled due to non- optimized barrier and oxide thickness (T OXE =4.6 nm) o Need to scale the barrier, oxide and quantum well thickness
Output Characteristics of Sb NMOS 500 600 V GS Start=0.5V 200 V GS Start=0.5V V GS Start=0.5V 500 400 Step=-0.25V Step=-0.25V Step=-0.25V 150 L G =5 µ m L G =450nm L G =150nm I D [ µ A/ µ m] 400 I D [ µ A/ µ m] I D [ µ A/ µ m] 300 300 100 200 200 50 100 100 0 0 0 0.0 0.5 1.0 0.0 0.5 1.0 0.0 0.5 1.0 Drain Voltage [V] Drain Voltage [V] Drain Voltage [V] Excellent saturation (at low V G ) in the output characteristics for long L G device I DSAT of 450 µA/µm at 0.75 V V DS for 150 nm L G device Short channel I ON limited by contact resistance
Long Channel Transport 2 /Vs] Hall Mobility 10 4 As Grown Drift Mobility [cm InAsSb 3x QW MOSFET 15x 10 3 In 0.53 Ga 0.47 As MOSFET S. Takagi, IEDM 2011 Si/SiO 2 10 11 10 12 -2 ] Carrier Density [/cm Record high electron drift mobility of 6,000 cm 2 /Vs at 2x10 12 /cm 2 of N s Drift mobility lower than measured Hall mobility of QW layers by 2.2x o Measured C-V overestimates the charge density due to D it o Scattering from high- κ phonons or surface charge at oxide interface
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