III-V CMOS: Quo Vadis? J. A. del Alamo, X. Cai, W. Lu, A. Vardi, and - PowerPoint PPT Presentation

III-V CMOS: Quo Vadis? J. A. del Alamo, X. Cai, W. Lu, A. Vardi, and X. Zhao Microsystems Technology Laboratories Massachusetts Institute of Technology EUROSOI-ULIS 2018 Granada, Spain, March 19-21, 2018 Acknowledgements: • Former students and collaborators: D. Antoniadis, E. Fitzgerald, J. Lin • Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman, NSF, Samsung, SRC • Labs at MIT: MTL, EBL

Quo Vadis? = Where are you going? 2

III-V CMOS: The Promise Scaling: Voltage ↓  Current density ↓  Performance ↓ Current density of n-MOSFETs Source injection velocity: Si vs. at nominal voltage: InGaAs FETs del Alamo, Nature 2011 v inj (InGaAs) > 2v inj (Si) at less than half V DD  high current at low voltage 3

Transconductance of Planar Si vs. InGaAs MOSFETs n-MOSFETs in Intel’s nodes at nominal voltage “Comparisons always fraught with danger…” MIT (V DS =0.5 V) • InGaAs exceeds Si Lin, IEDM 2014 • Rapid recent progress EDL 2016 4

Many requirements for a successful logic technology 1. ON current 2. OFF current 3. Scalability 4. Stability 5. Manufacturing robustness 6. Si integration 5

Transistor structure evolution for improved scalability Planar bulk Nanowire MOSFET MOSFET Thin-body SOI MOSFET FinFET Enhanced gate control  improved scalability 6

Transconductance of Si vs. InGaAs FinFETs 7

Transconductance of Si vs. InGaAs FinFETs 8

Transconductance of Si vs. InGaAs FinFETs W f g m normalized by fin width FinFET: large increase in current density per unit footprint over planar MOSFET 9

Transconductance of Si vs. InGaAs FinFETs W f MIT (V DS =0.5 V) g m normalized by fin width Best InGaAs FinFETs nearly match 14 nm Si MOSFETs 10

Transconductance of Si vs. InGaAs FinFETs 10 nm node Intel (V DS =0.7 V) W f g m normalized by fin width 10 nm node Si MOSFETs a great new challenge! 11

InGaAs FinFETs @ MIT Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch Vardi, • Sub-10 nm fin width DRC 2014, • Aspect ratio > 20 EDL 2015, • Vertical sidewalls IEDM 2015 12

InGaAs FinFETs @ MIT Mo Mo High‐K HSQ SiO 2 HSQ L g W/Mo High‐K n + ‐InGaAs InP InGaAs InGaAs δ ‐ Si InAlAs InP Vardi, IEDM 2017 • Si-compatible process • Contact-first, gate-last process • Fin etch mask left in place  double-gate MOSFET 13

Most aggressively scaled FinFET W f =5 nm, L g =50 nm, H c =50 nm (AR=10), EOT=0.8 nm: 1E-3 L g =50 nm V DS =500 mV V GS =-0.2 to 0.5 V W f =5 nm 1E-4 150  V GS =0.1 V 50 mV 1E-5 I d [A/  m] 100 1E-6 I d [  A/  m] S sat =75 mV/dec S lin =65 mV/dec 1E-7 50 1E-8 1E-9 -0.2 0.0 0.2 0.4 0.6 0.8 0 V GS [V] 0.0 0.1 0.2 0.3 0.4 0.5 700 V DS =0.5 V g m,max =565 µS/µm V GS [V] Normalized by 600 L g =50 nm conducting gate 500 W f =5 nm At V DS =0.5 V: periphery = 2H c g m [  S/  m] 400 • g m =565 µS/µm 300 200 • R on =660 Ω.µm 100 • S sat =75 mV/dec 0 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 • DIBL=22 mV/V Vardi, IEDM 2017 V GS [V] 14

Fin-width scaling of ON-state current 2.0 Vardi, IEDM 2017 1.5 g m [mS/  m] in planar 1.0 MOSFETs expect L g =40-60 nm 2.2 mS/µm 0.5 V DS = 0.5 V 0.0 0 5 10 15 20 25 W f [nm] Normalized by conducting 1000 gate periphery = 2H c 800 • g m independent of W f down 600 R on [  -  m] to W f =7 nm • In planar MOSFET (x=0.53) 400 expect g m ~ 2.2 mS/µm 200 • Missing performance hints 0 0 5 10 15 20 25 at sidewall damage W f [nm] 15

Fin-width scaling of OFF-state current S sat (V DS = 0.5 V) 120 S sat 1E-3 L g =50 nm V DS =500 mV S lin W f =5 nm 1E-4 50 mV 100 1E-5 S [mV/dec] I d [A/  m] 80 1E-6 S sat =75 mV/dec S lin (V DS = 50 mV) S lin =65 mV/dec 1E-7 60 1E-8 L g =40-60 nm 1E-9 -0.2 0.0 0.2 0.4 0.6 0.8 40 0 5 10 15 20 25 V GS [V] W f [nm] • Excellent subthreshold swing scaling behavior • From long L g devices: D it ~ 8x10 11 cm -2 .eV -1 Vardi, IEDM 2017 16

Excess OFF-state current Band-to-band tunneling (BTBT) at drain end of channel Zhao, EDL 2018 Classic BTBT behavior in long-channel devices 17

Excess OFF-state current Current multiplication through parasitic bipolar transistor -1 slope • Large BJT current gain (up to ~100) • Short L g : β ~ 1/L g • Long L g : β ~ exp(-L g /L d ), L d ≈ 2-4 µm Zhao, EDL 2018 18

Manufacturing robustness: impact of fin width on V T InGaAs doped-channel FinFETs: 50 nm thick, N D ~10 18 cm -3 Vardi, IEDM 2015 T=90K • Strong V T sensitivity for W f < 10 nm; much worse than Si • Due to quantum effects • Big concern for future manufacturing 19

MOSFET threshold voltage stability Planar InGaAs MOSFETs under forward-gate stress: 2.5 nm HfO 2 • ∆V t : power law in time and stress voltage • Typical of PBTI (Positive Bias Stress Instability) Cai, IEDM 2016 20

MOSFET stability due to oxide traps Planar InGaAs MOSFETs under forward-gate stress: V gt =0.4 V 9 10  g m,max /g m,max (%) time to 30mV shift (s) V gt,stress @ 10 years 0 1.1 V 7 10 1.0 V -10 0.8 V 0.6 V 5 10 -20 3 10 -30 1 10 Cai, IEDM 2016 0.4 0.6 0.8 1 1.2 0.00 0.05 0.10 V gt,stress (V)  V t, lin (V) • 30 mV shift in 10 years for V gt = 0.4 V • Strong correlation between ∆g max and ∆V t,lin at different V gt,stress • Due to border traps in HfO 2 Excellent review in Franco, IEDM 2017 21

Other manifestations of oxide traps C-V frequency dispersion g m frequency dispersion Pulsed vs. DC Cai, CSW 2018 Also: Johansson, ESSDERC, 2013 • Frequency dispersion in C g and g m • Pulsed I-V ≠ DC I-V Also: Cartier, ESSDERC 2017 22

Important consequences Confusing characterization: i.e. mobility-field relationship by 1 MHz C-V and Hall effect: In 0.7 Ga 0.3 As Oxide trapping:  N s overestimated  µ e underestimated Cai, CSW 2018  µ e -N s relationship distorted 23

InGaAs Vertical Nanowire MOSFETs VNW MOSFET Vertical NW MOSFET:  uncouples footprint scaling from L g , L spacer , and L c scaling 24

InGaAs VNW-MOSFETs by top-down approach @ MIT Lu, EDL 2017 • Top-down approach: flexible and manufacturable • Critical technologies: precision RIE + alcohol-based digital etch 25

D=7 nm InGaAs VNW MOSFET 800 V gs = 0 V to 0.8 V in 0.1 V step -3 V ds =0.5 V 10 D = 7 nm 700 D = 7 nm -4 10 600 -5 10 I d  A/  m) 500 V ds =0.05 V I d ( A/  m ) -6 400 10 300 -7 10 S lin /S sat = 85/90 mV/dec 200 -8 10 DIBL = 222 mV/dec 100 -9 10 0 -0.2 0.0 0.2 0.4 0.6 0.0 0.1 0.2 0.3 0.4 0.5 V gs (V) V ds (V) V ds =0.5 V Single nanowire MOSFET: 1800 g m,pk = 1700  S/  m Ni contact • L ch = 80 nm 1400 D = 7 nm g m (  S/  m ) o C FGA 200 • 2.5 nm Al 2 O 3 (EOT = 1.3 nm) 1000 • g m,pk =1700 µS/µm 600 • Top contact = key problem 200 Before FGA V ds =0.5 V -0.2 0.0 0.2 0.4 0.6 Zhao, IEDM 2017 V gs (V) 26

Benchmark with Si/Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs MIT @ V DS =0.5 V Zhao, IEDM 2017 • First sub-10 nm diameter VNW FET of any kind on any material system • InGaAs competitive with Si [hard to add strain] 27

InGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Vapor-Solid-Liquid Selective-Area Epitaxy (SAE) (VLS) Technique Riel, MRS Bull 2014 VNW MOSFETs: path for III-V integration on Si for future CMOS Riel, IEDM 2012 28

Conclusions 1. Great recent progress on planar, fin and nanowire InGaAs MOSFETs 2. Device performance still lacking for 3D architecture designs 3. Serious challenges identified: excess off-current, stability, manufacturability, integration with Si 4. Vertical Nanowire MOSFET: ultimate scalable transistor; integrates well on Si 29

Mobility scaling with fin-width Mobility extraction using C-V measurements at 1 GHz: 1500 n l = 3x10 7 cm -1 V GT ~ 0.4 V 1000 2 /Vsec]  [cm 500 Undoped Poisson-Schrodinger 0 simulations 5 10 15 20 25 W f [nm] • Poor mobility for wide W f • In planar MOSFET (x=0.53, EOT= 0.8 nm) expect µ ~ … cm 2 /V.s • Severe mobility degradation as W f ↓ • Onset of degradation: W f ~ 20 nm  sidewall damage? Vardi, IEDM 2017  line edge roughness? 30

Channel thickness scaling of planar InGaAs MOSFETs Planar MOSFETs (x=0.7, L g =200 nm) • Severe g m degradation as t c ↓ • Onset of degradation: t c < 6 nm Cai, CSW 2018 31

InGaAs VNW MOSFETs: Output characteristics vs. diameter D = 7 nm D = 15 nm D = 30 nm 800 800 800 V gs = 0 V to 0.8 V in 0.1 V step V gs = 0 V to 0.8 V in 0.1 V step V gs = 0 V to 0.8 V in 0.1 V step 700 700 700 600 600 600 I d  A/  m) 500 I d  A/  m) 500 I d  A/  m) 500 400 400 Ni 400 300 300 300 200 200 200 100 100 100 0 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) V ds (V) V ds (V) 800 800 V gs = 0 V to 0.8 V in 0.1 V step 800 V gs = 0 V to 0.6 V in 0.1 V step V gs = 0 V to 0.7 V in 0.1 V step 700 700 700 600 600 600 I d (  A/  m) 500 I d  A/  m) 500 I d  A/  m) 500 Mo 400 400 400 300 300 300 200 200 200 100 100 100 0 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) V ds (V) V ds (V) Top contact is key challenge in VNW MOSFETs 32