I 2 C-bus Elements SASE March 2010 SASE- March 2010 Alix Maldonado -Technical Marketing Manager Product Line System Management Business Line Interface Products
Agenda I 2 C-bus Protocol Electrical Characteristics Electrical Characteristics Measurements with an Oscilloscope Resources Questions 2
I 2 C - Protocol IIC - Inter-Integrated Circuit g Logic Logic This means: • Decreased number of wires (reduced PCB area) • Reduced number of chip pins p p • Remove glue logic I 2 C-bus • Clip many devices on to the bus • Modular design: Time-to-Market V V CC Invented by NXP! (Philips Semiconductors) (Philips Semiconductors) I 2 C-bus developed in the late 1970’s for Philips consumer products (e.g. TVs) Worldwide industry standard and used by all major IC manufacturers Worldwide industry standard and used by all major IC manufacturers 3
I 2 C - Protocol Hardware architecture V DD Pull up resistors SDA SDA SCL Clock out Data out Clock out Data out Clock in Data in Clock in Data in Device 1 Device 2 2 wire bus: – SDA : Serial Data Line SDA : Serial Data Line – SCL : Serial Clock Line Open-drain or open-collector output stages: wired-AND function 4
I 2 C - Protocol Hardware architecture (2) Master2 Slave2 V DD SDA SCL Master1 Slave1 Multiple master Multiple slave Bi-directional – Master-transmitter – Master-receiver – Slave-transmitter – Slave-receiver Data collision is taken care off Data collision is taken care off 5
I 2 C - Protocol Addressing / device selection Each device is addressed individually by software New devices or functions can be easily “clipped" on to an existing bus! 112 different addresses max with the 7-bit format (others reserved); additional 1024 with ( ) 10-bit format Address allocation coordinated by the I 2 C-bus committee Programmable pins means that several of the same devices can share the same bus Unique address per device: fully fixed or with a programmable part through hardware f f pin's) 10-bit format use a 2 byte message: 1111 0A 9 A 8 R/W + A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 V V DD SDA SCL Master1 Slave1 Address register Fixed A6 A5 A4 A3 A2 A1 A0 V DD 0 0 1 1 1 0 0 Hardware Programmable 6
I 2 C - Protocol Master Communication Slave Communication must start with: START condition Start bit is always followed by slave address Master or Slave Slave address is followed by a READ or NOT-WRITE bit Sl dd i f ll d b READ NOT WRITE bit The receiving device (either master or slave) must send an ACKNOWLEDGE bit Communication must start with: STOP condition SLAVE START R/W ACK DATA[8] ACK STOP ADDRESS[7] Example: Example: Transmit (0 = Write) SLAVE START 0 ACK DATA[8] ACK DATA[8] ACK STOP ADDRESS[7] Receive (1 = Read) SLAVE START 1 ACK DATA[8] ACK DATA[8] ACK STOP ADDRESS[7] 7
I 2 C - Protocol START & STOP conditions Start condition - a HIGH to LOW transition on the SDA line while SCL is HIGH Stop condition - a LOW to HIGH transition on the SDA line while SCL is HIGH 8
START Timing Diagram START condition is a high to low transition on the SDA line while SCL is high RE- Slave … DATA START R/W ACK DATA ACK NACK START/ Address STOP STOP 9
STOP Timing Diagram STOP condition is a low to high transition on the SDA line while SCL is high RE- Slave … DATA START R/W ACK DATA ACK NACK START/ Address STOP STOP 10
RE-START Timing Diagram RESTART condition is a high to low transition on the SDA line while SCL is RESTART diti i hi h t l t iti th SDA li hil SCL i high, exactly the same as the START RE- Slave … DATA START R/W ACK DATA ACK NACK START/ Address STOP STOP 11
12 During data transfer, SDA must be stable when SCL is High I 2 C - Protocol Bit transfer
I 2 C - Protocol Data transfer Each byte has to be followed by an acknowledge bit Number of data bytes transmitted per transfer is unrestricted If a slave can’t receive or transmit another complete byte of data, it can hold the clock line SCL LOW (clock stretching) to force the master into a wait state 13
I 2 C - Protocol Acknowledge / NOT-Acknowledge I 2 C specification: Data transfer with acknowledge is obligatory. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW d during the HIGH period of this clock pulse. i th HIGH i d f thi l k l Scenarios with a NOT-acknowledge (NACK) (SDA staying HIGH): A receiver with the address is not present in the I 2 C bus. 1. The receiver is performing real-time tasks and it cannot process the received I 2 C 2 2. The receiver is performing real time tasks and it cannot process the received I C information. 3. The receiver is the master and wants to take control of SDA line again in order to generate a STOP command. The slave transmitter MUST then release the SDA line when it sees the NACK so the master can send the STOP command line when it sees the NACK so the master can send the STOP command. 14
I 2 C - Protocol Arbitration procedure p Two or more masters may generate a START V DD condition at the same time SDA Arbitration is done on SDA while SCL is HIGH - Slaves are not involved Sl i l d DATA1 DATA2 SDA SDA Master 1 Master 2 Summary: The master that first sends a “1” while the other sends a “0” loses control (arbitration) 15
I 2 C - Protocol Clock synchronization during the arbitration procedure y g p V DD Internal counters of masters count the LOW and HIGH times (T L1 , T H1 ) and (T L2 , T H2 ) SCL CLK1 CLK2 SCL SCL SCL SCL Master 1 Master 2 T T L1 T T H1 Wired-AND SCL connection: T L = longest T L = max (T L1 , T L2 ,T Ln ) T L2 T H2 T T H = shortest T H = min (T H1 , T H2 ,T Hn ) shortest T min (T T T ) L2 H2 T T L T T H 16
I 2 C - Protocol Modes Fast Mode Plus High Speed Mode Standard Mode Fast Mode (FM+) (FM+) Bitrate (kBit/s) 0 – 100 0 – 400 0 – 1000 0 – 1700 0 – 3400 Address (bits) 7 (10) 7 (10) 7 (10) 7 (10) 7 (10) Capacitive Bus Load (pF) 400 400 550 400 100 Sink current (mA) 3 3 20 3 3 Fast mode Plus (FM+): – Increased bandwidth Increased bandwidth – Increased transmission distance (at reduced bandwidth: >> 550 pF bus load) 17
I 2 C - Protocol Modes: Electrical specification Fast Mode Plus Standard Mode Fast Mode High Speed Mode (FM+) Bitrate (kBit/s) 0 – 100 0 – 400 0 – 1000 0 – 1700 0 – 3400 Address (bits) 7 (10) 7 (10) 7 (10) 7 (10) 7 (10) Capacitive Bus Load (pF) 400 400 4000 400 100 Sink current (mA) 3 3 20 3 3 Trise: Rise time (ns) Trise: Rise time (ns) 1000 1000 300 300 120 120 160 160 80 80 t rise V cc V IH V 0.7 * V DD V bus (V) V V IL 0 3 * V 0.3 V DD V OL gnd t 1 t 2 t (s) 0.4 V @ 3 mA sink current 0 4 V @ 20 mA sink current (FM+) 0.4 V @ 20 mA sink current (FM+) 18
I 2 C - Protocol Summary START HIGH to LOW transition on SDA while SCL is HIGH STOP LOW to HIGH transition on SDA while SCL is HIGH 8-bit word, MSB first (Address, Control, Data): - Must be stable when SCL is HIGH DATA - Can change only when SCL is LOW - Number of bytes transmitted is unrestricted - Done on each 9th clock pulse during the HIGH period D h 9th l k l d i th HIGH i d ACKNOWLEDGE - The transmitter releases the bus - SDA goes HIGH - The receiver pulls DOWN the bus line - SDA goes LOW - Generated by the Master(s) - Maximum speed: (100, 400, 1000, 3400 kHz) but NO min p ( ) CLOCK CLOCK - A receiver can hold SCL low when performing another function (transmitter in a Wait state) - A master can slow down the clock for slow devices - Master can start a transfer only if the bus is free - Several masters can start a transfer at the same time ARBITRATION - Arbitration is done on SDA line A bit ti i d SDA li - Master that lost the arbitration must stop sending data 19
START and STOP Conditions START and STOP Conditions Q estion What is Question: What is wrong with this figure? rong ith this fig re? 20
Data Transfer Acknowledge Data • During data transfer SDA must be stable when SCL is High During data transfer, SDA must be stable when SCL is High • Each byte has to be followed by an acknowledge bit • Number of bytes transmitted per transfer is unrestricted • If a slave can’t receive or transmit another complete byte of data, it can hold the clock line SCL LOW to force the master into a wait state master into a wait state 21
I 2 C-bus Slave Address (1) Two formats of I 2 C slave address: 7-bit or 10-bit address 7-bit Slave address is most popular, allows up 111(2 7 = 128 devices � 128 – 17 reserved ) 10-bit slave address may accommodate up to 2 10 = 1024 devices on the same bus Devices that supports either 7 bit or 10 bit address may co exist on the same Devices that supports either 7-bit or 10-bit address, may co-exist on the same bus Reserved Addresses RE- RE- ACK/ Slave Slave START START R/W R/W … … ACK ACK DATA DATA ACK ACK NACK NACK START/ START/ DATA DATA Address Address STOP STOP STOP STOP 22
Recommend
More recommend
