High Speed and Low-Power SerDes Architectures using Chord Signaling - PowerPoint PPT Presentation

Noise Mitigation Common Mode noise, EMI noise, SSO, and reference noise can be dealt with one elegant construction.

Common Mode Noise a a + x b b + x c c + x Common mode noise d d + x e e + x • Bad for signal integrity • Common mode should be rejected at receiver Means that comparators should evaluate to 0 on vector (1,1,1,...,1) • Codewords should have no common mode component Common mode component is along vector (1,1,1,...,1) Means that the sum of the values on the wires should be constant.

CM Resistance Differential Signaling ~ x b + sgn( x- y) ~ -b - y

CM Resistant Codes Differential Signaling Orthogonal space Codewords should be on this line (-1,1) Common mode direction (1,-1)

Differential from Single Ended Orthogonal space Codewords should be on this line (-1,1) Common mode direction (1,-1) Orthogonal Transformation

Tempering Process • Creates CM resistant Chordal code from any Chordal code • The number of wires of the interface grows by one • All other parameters of the code stay the same (including the ISI ratio) • Use Tempering Orthogonal Transformation on the codewords. * * * * * * * * * * * * * 0 * * * * * * 0 + + + + + = * * * * * * 0 * * * * * * 0 * * * * * * 0 Orthogonal matrix Tempering orthogonal matrix • (0 | old codeword) * Tempering Orthogonal Matrix = new codeword • (0 | old comparator) * Tempering Orthogonal Matrix = new comparator

Examples ENRZ + -   ± (1 , − 1 / 3 , − 1 / 3 , − 1 / 3) 1 1 1 1 1 ± ( − 1 / 3 , 1 , − 1 / 3 , − 1 / 3) 1 − 1 1 − 1   +   - 1 1 − 1 − 1 ± ( − 1 / 3 , − 1 / 3 , 1 , − 1 / 3) 2   1 − 1 − 1 1 ± ( − 1 / 3 , − 1 / 3 , − 1 / 3 , 1) Hadamard Transform + - ACTUAL IMPLEMENTATION MAY BE DIFFERENT

Common Mode Noise Disappears by construction. Chord Signaling Chord Signaling Single-ended Differential 4-PAM diff. Single-ended Differential 4-PAM diff. (so far) (so far) - + +/- - SSO - + +/- - SSO - + - - Ref - + - - Ref - + + - EMI - + + - EMI Common - + + - Common - + + + mode mode + - - - + ISI + - - - + ISI High speed Pin count High speed High speed Pin count High speed May have issues Conclusion May have issues Conclusion problematic problematic issues problematic problematic issues

Reference Noise Disappears, since no reference needed. Chord Signaling Chord Signaling Single-ended Differential 4-PAM diff. Single-ended Differential 4-PAM diff. (so far) (so far) - + +/- - SSO - + +/- - SSO - + - - Ref - + - + Ref - + + - EMI - + + - EMI Common - + + + Common - + + + mode mode + - - - + ISI + - - - + ISI High speed Pin count High speed High speed Pin count High speed May have issues Conclusion May have issues Conclusion problematic problematic issues problematic problematic issues

EMI Noise Largely mitigated, since sum of currents on the wires is 0 (far- fields cancel each other). Will talk about it later. Chord Signaling Chord Signaling Single-ended Differential 4-PAM diff. Single-ended Differential 4-PAM diff. (so far) (so far) - + +/- - SSO - + +/- - SSO - + - + Ref - + - + Ref - + + + EMI - + + - EMI Common - + + + Common - + + + mode mode + - - - + ISI + - - - + ISI High speed Pin count High speed High speed Pin count High speed May have issues Conclusion May have issues Conclusion problematic problematic issues problematic problematic issues

Chord SSO Signaling Noise Largely mitigated through additional constraint on tempering matrix. Single-ended Differential 4-PAM diff. Chord Signaling Chord Signaling - + +/- + SSO SSO + - + - + Ref Ref + - + + + EMI EMI + Common Common - + + + + mode mode + - - - + ISI ISI + High speed Pin count High speed Can be used in a wide Conclusion Conclusion problematic problematic issues range of applications

Chordal Code Definition A ( n, N, c, I )- Chordal Code (CC) is a pair where ( C, Λ ) ‣ C is a subset of of size N (set of codewords) [ − 1 , 1] n ‣ is a subset of of size c (set of comparators) ( R n ) ∗ Λ such that ‣ (Distinguishability) 8 c 1 , c 2 2 C, c 1 6 = c 2 9 λ 2 Λ : λ ( c 1 ) λ ( c 2 ) < 0 | λ ( c 1 ) | ‣ (ISI-tolerance) ∀ λ ∈ Λ , c 1 , c 2 ∈ C : | λ ( c 2 ) | ≤ I Lots of practical concerns swept under the rug. Given n and N, find minimum I , such that there exists a ( n, N, c, I )-CC for some c.

Chordal Code Definition A ( n, N, c, I )- Chordal Code (CC) is a tuple where ( C, Λ , I ) ‣ C is a subset of of size N (set of codewords) ISI-ratio [ − 1 , 1] n ‣ is a subset of of size c (set of comparators) ( R n ) ∗ Λ Detection complexity ‣ is a subset of (set of inactives) I C × Λ Number of codewords Number of wires such that ‣ (Distinguishability) 8 c 1 , c 2 2 C, c 1 6 = c 2 : 9 λ 2 Λ , ( c 1 , λ ) , ( c 2 , λ ) 62 I : λ ( c 1 ) λ ( c 2 ) < 0 log 2 ( N ) 8 λ 2 Λ 8 c 1 , c 2 2 C, ( c 1 , λ ) , ( c 2 , λ ) 62 I : | λ ( c 1 ) | Rate, or pin-efficiency ‣ (ISI-tolerance) | λ ( c 2 ) | ≤ I n Lots of practical concerns swept under the rug.

(Trivial) Bounds For a ( n, N, c, I )- CC we have: • c ≥ n (every comparator gives at most one bit of information) | λ ( c 1 ) | ⇒ | λ ( c 2 ) | | λ ( c 1 ) | ≥ 1 • I ≥ 1: | λ ( c 2 ) | ≤ I = I n − 1 ✓ c ◆ � X 1 + ( − 1) n − 1 − i � • N ≤ (Zaslavsky’s formula) i i =0

Example of a Concrete Question What is the best ISI-ratio for n = 3, N = 16? Best result so far: 2.39304, 11 comparators, not practical

A Conjecture ( n, N, c, I ) − CC = ⇒ N ≤ (1 + I ) n

Electromagnetic Interference (EMI) Noise

Electromagnetic Interference (EMI) First order analysis of strength of the Electric far-field generated by a charge loop Area = A Far field strength ~ f 2 · I · A Frequency = f Current = I Fix all parameters to 1 for a baseline computation. Then far-field has FOM = 1.

EMI Differential signaling: +1 -1 -1 +1 FOM = 1 FOM = -1 Average strength = (1+|-1|)/2 = 1

Electromagnetic Interference Two differential lanes: - + + - + - + - 0 0 -2 2 Average strength = (2+|-2|)/4 = 1

Electromagnetic Interference -c 1 -c 2 -c 3 - c 4 - c 5 c 1 + c 2 + c 3 + c 4 + c 5 General form: c 1 + c 2 + c 3 + c 4 + c 5 c 0 + -c 2 -c 3 - c 4 - c 5 + c 1 c 2 + c 3 + c 4 + c 5 c 2 + c 3 + c 4 + c 5 + c 2 + -c 3 - c 4 - c 5 c 3 + c 4 + c 5 c 3 c 3 + c 4 + c 5 + c 4 -c 4 - c 5 + c 4 + c 5 c 4 + c 5 c 5 + -c 5 + c 5 c 5

Electromagnetic Interference -c 1 -c 2 -c 3 - c 4 - c 5 c 1 + c 2 + c 3 + c 4 + c 5 General form: c 1 + c 2 + c 3 + c 4 + c 5 + -c 2 -c 3 - c 4 - c 5 + c 2 + c 3 + c 4 + c 5 c 2 + c 3 + c 4 + c 5 + + c 1 +2 c 2 +3 c 3 +4 c 4 +5 c 5 c’ (1) -c 3 - c 4 - c 5 c 3 + c 4 + c 5 c 3 + c 4 + c 5 + -c 4 - c 5 + c 4 + c 5 c 4 + c 5 + -c 5 + c 5 c 5

Electromagnetic Interference FOM for a code C in which for all codewords sum of coordinates is zero: 1 X | c 0 (1) | | C | c 2 C

Examples Two differential lanes: 1 4 (2 + | − 2 | ) = 1 ENRZ: FOM = (2+2/3)/2 = 4/3 ± (1 , − 1 / 3 , − 1 / 3 , − 1 / 3) → 2 ± ( − 1 / 3 , 1 , − 1 / 3 , − 1 / 3) → 2 3 ± ( − 1 / 3 , − 1 / 3 , 1 , − 1 / 3) → 2 3 ± ( − 1 / 3 , − 1 / 3 , − 1 / 3 , 1) → 2 Equal throughput: differential runs at 1.5 times the frequency. Throughput-normalized FOM: Differential: (1.5) 2 = 2.25 ENRZ: 4/3 ~ 1.33 SMALLER!

E-Field of ENRZ DS ENRZ

Summary • Chord Signaling (Chordal Coding) provides a mathematically concise framework for the design of noise resilient modulation schemes for chip-to-chip communication. • From a theoretical point of view the main question is to construct for a given number of wires and a given ISI-ratio chordal codes of that ratio that have the maximum number of codewords. • One optimal class (of ISI-ratio 1) of is provided by applying the the tempering construction to the hypercube. • The definition of a chordal code given above can be extended in different ways (not subject of current presentation).

High Speed and Low-Power SerDes Architectures using Chord Signaling Part 2: APPLICATIONS Amin Shokrollahi In collaboration with the Engineering Team of Kandou Bus

Digital Design, Shannon He asked • How to analyse switch network circuits • How to synthesise switch network circuits efficiently And he provided answers! Claude Elwood Shannon 1916 - 2001 Father of digital design, at least 20 years ahead of his ?me MSc Thesis, MIT, 1937

Bell Laboratories Aerial view of Bell Labs in Murray Hill http://users.ece.gatech.edu/~juang/B%20JUANG%20Georgia%20Tech%20Pictures.html

Invention of the Transistor (End of 1947) First Transistor Bardeen, Shockley, and Brettain, 1948 Received the Nobel Prize in Physics in 1956

Integrated Circuits • Discrete transistors were di ffi cult to connect - Too many wires • The next big idea was the use of “integrated circuits - Put all the electronic ARMv6 processor circuits onto one small plate of semiconductor material (typically silicon) - The entire circuit can be made much smaller • Today manufacturing uses the process of optical lithography http://www.just2good.co.uk/cpuSilicon.php

Transistors: Size, Speed, and Power A y y A √ 2 2 x x √ 2 Reduc?on in size reduces effec?ve capacitance by 1 √ 2 Reduc?on in capacitance reduces device delay by same factor 1 TD TD TD T D reduced by implies frequency 1/(3*T D ) is √ Ring oscillator 2 increased by √ 2 To keep constant electrical field, voltage is mul?plied by 1 √ 2

Transistors: Size, Speed, and Power A y y A √ 2 2 x x √ 2 1 Reduc?on in feature size by √ 2 • Allows for packing 2 x number of transistors • Decreases voltage by 30% • Increases speed by 40%

Gordon Moore and his Law Gordon Moore 1929 - Electronics Magazine 1965

Moore’s Foresight Figure 2 in Moore’s paper http://www.businessinsider.com/munster-iphone-lines-launch-day-2013-9?IR=T https://www.wsj.com/articles/apple-store-lines-return-as-iphone-x-debuts-1509683635 https://www.gottabemobile.com/why-you-shouldnt-bother-lining-up-for-the-iphone-x-and-iphone-8/

Transistors: Size, Speed, and Power Processor Transistor count Manufacturer Transistor pitch ARM-1 25'000 ARM Holdings 3000 nm Intel i-960 250'000 Intel 600 nm Pentium Pro 5'500'000 Intel 500 nm Pentium III 45'000'000 Intel 130 nm PC’s Pentium 4 184'000'000 Intel 65 nm iPhone 5S Apple A7 1'000'000'000 Apple 28 nm iPhone 6 Apple A8 2'000'000'000 Apple 20 nm Xeon Haswell 5'560'000'000 Intel 22 nm Gaming Fiji (GPU) 8'900'000'000 AMD 28 nm

15.00 22.50 30.00 0.00 7.50 1974 1976 1977 1978 1980 1982 1984 Moore’s Law against Reality 1985 1986 1988 Actual 1989 1990 1992 1994 1995 1997 1999 2001 2004 2006 Moore’s law 2008 2010 2012 2014 2017 2018 2020 2022 2024 2026 2028

Andreas Bechtolsheim 1955 - CPU: 64X/12Y Performance GigE: 10X/12Y Moore’s Law doesn’t hold for I/O Routers: 4X/12Y Time

Data Explosion “In 2008 the “IP datacenter “The amount of data is “Monthly world’s 27 million traffic will be 8.6 doubling every 24 months, global mobile business servers zettabytes by 2018” and will reach 44 data traffic will processed 9.57 – Cisco forecast, zettabytes (4.4 x 10 22 surpass 24.3 zettabytes” – 2013 bytes) by 2020” – IDC, 2014 exabytes (2.4 x 10 18 bytes) by Computerworld, 2011 2019” – Cisco forecast, 2015

Interconnect Problem THE bottleneck the industry is facing

Shannon, again

Shannon, for Wireline Communication 400G Target Throughput 20x Today 20G Noise How do we get there?

Secret of getting close to Capacity (wireless, DSL, AdC? ADC Way too much power consump?on in wireline world at super high speeds (at least up un?l now).

Challenge Design an approximate ADC that works in this se[ng

Chord Signaling w 0 0 b 0 + 1 b 0 - w 1 2 + 0 b 1 b 1 - av 1 w 2 Rx frontend Encoder 0 1 av b 2 + 2 b 2 3 w 3 - av 4 5 b 3 3 + w 4 b 3 4 - av 5 b 4 4 w 5 + b 4 - 5 Much be\er u?lisa?on of communica?on bandwidth using “MIMO” like techniques (without an elaborate ADC)

Moore’s Paper, again Massive “integra?on” on chip (SoC’s) is running its course

Massive Disintegration with Glasswing Photonics Photonics Photonics Photonics Photonics (SiGe) (SiGe) (SiGe) (SiGe) (SiGe) Photonics Photonics Photonics Photonics Photonics (SiGe) (SiGe) (SiGe) (SiGe) (SiGe) Glasswing Glasswing Memory interface Glasswing Glasswing Glasswing Glasswing SoC/2 Analog DRAM Glasswing System on Chip Glasswing SoC Memory interface Glasswing Glasswing Glasswing Glasswing SoC/2 DSPs DRAM Glasswing Glasswing Long-reach Long-reach Long-reach Long-reach Long-reach SerDes SerDes SerDes SerDes SerDes Long-reach Long-reach Long-reach Long-reach Long-reach SerDes SerDes SerDes SerDes SerDes Lifeline for Moore’s law: low cost integra?on of func?onality