High Performance New drivers Requirements Solutions - PowerPoint PPT Presentation

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High Performance New drivers Requirements Solutions Computing New workloads More computing performance (Ops Heterogeneity: per second), also for simple Generic processing Compute operations (FP16, FP8, INT…). + accelerators Energy efficiency (Ops per Watt). Low power design Analyze Massive volume Increased Bytes per Flops. High Bandwidth of data High bandwidth/low latency access Memories and 2.5D to all data. integration Data in Data out • Starting from high < 10x energy efficiency performance compute only, improvement every 4 years HPC evolves towards: • New workloads • Massive volume of data TERA1000 - CEA

Far NIC Mem. Generic processing Performance = ~nb cores High Speed Link Close Close Mem Mem. Performance = ~frequency Close Close Cache Cache Mem Mem NoC + LLC CPU Cache Cache Cache HW accelerator Bus NIC Memory Performance = ~architecture X86 cores, RISC cores, Co-pro extension, Accelerator, GPU, FPGA, Memory Real Time processing, Homogeneous, Heterogeneous, Data centric … NIC (Network  InterConnect)

Japan K / RIKEN, 2011 (2020-2021) SPARC64 VIIIfx Fugaku / RIKEN  11.28 petaflops (peak) A64FX (Armv8.2+SVE) 10.51 petaflops >0.5 exaflops  Sunway TaihuLight /NRCPC (?) China NRCPC Exa-prototype SW26010 ?  SW26010 based 125.43 petaflops (peak) ? homogeneous (2020-2021) Tianhe-2 /NUDT, 2013 Tianhe-2a /NUDT, 2018 Tianhe-3 / NUDT  Intel Xeon + KNC Intel Xeon + Matrix-2000 Matrix-3000 33.86 petaflops (peak) 94.97 petaflops (peak) >1.0 exaflops (peak) (?) Sugon Exa-prototype Hygon CPU + DCU Hygon CPU + DCU ? Europe approach ? US (2021) Aurora / ANL Summit / ORNL, 2019 Intel Xeon + Xe IBM P9 + NVidia GPU >1.0 exaflops (peak) 200 petaflops (peak) (2021) 148.6 petaflops Sierra / LLNL, 2019 Frontier / ORNL IBM P9 + NVidia GPU AMD CPU + GPU ~1.5 exaflops (peak) 125 petaflops (peak) heterogeneous, accelerated

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GPP processor chip  Security infrastructure  Power Management infrastructure Real-time processing  Generic Accelerator processing  eFPGA

METHODOLOGY Architects PCIe Ie gen5 HSL + Application links links Co-design Model and Experts simulation ARM ARM MPPA D2D links HBM HBM to adja jacen ent chipl plet ets memorie ies eFPGA EPAC COMPUTING UNITS SOFTWARE  Automotive eHPC Programming tools &  software support Libraries Low-level Software, Security, Power Management DDR DDR Linux Operating System  memorie ies EPI Processor and Reference Hardware 

PCIe Ie gen5 CCIX IX   links links D2D links to adja jacen ent chipl plet ets ARM ARM MPPA  eFPGA EPAC HBM HBM memories DDR DDR  memorie ies

PCIe Ie gen5 HSL links links ARM ARM MPPA D2D links HBM HBM to adja jacen ent chipl plet ets memorie ies eFPGA EPAC  DDR DDR memorie ies

 EPAC  VPU  Bridg dge e to GPP STX  VRP Bridg dge e to GPP

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Autom omotive otive Safet fety/ y/secu security ity MCU MCU

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