High Performance Cognitive Radio Platform with Integrated Physical & Network Layer Capabilities Bryan Ackland, Ivan Seskar WINLAB, Rutgers University bda@winlab.rutgers.edu seskar@winlab.rutgers.edu www.winlab.rutgers.edu 1
Dynamic Spectrum Allocation � Large, increasing demand for wireless services � Static frequency bands allocated to single service � Inefficient use of spectrum � Slow, expensive political process � Locally optimized incompatible solutions � FCC exploring alternatives � ISM & U-NII bands � Power and BW limitations to allow co-existence � Successful but quickly getting congested � Intelligent or “Cognitive” radios that adapt to local wireless environment � Improve spectrum efficiency and fairness 2
Cognitive Radio � Programmable radio systems that adapt to: � Changing radio interference � Availability of nearby collaborative nodes � Changing protocols & standards � Application requirements � by modifying � Frequency, power, bandwidth � Modulation, coding, MAC � Network protocols � and coordinating with other cognitive systems to maximize spectral efficiency and fairness 3
Cognitive Radio Implementation � Tradeoff between flexibility, performance & power flexibility speed, power, cost Silicon area efficiency 1 10 100 1000 Microprocessor ASIC DSP FPGA � “Moore’s Law” improvements in CMOS VLSI � Implement some functions in SW � Ultimate goal: software radio?? µ P A/D � Reality: some combination of HW, SW and reconfigurable logic 4
Programmable Wireless Networks Research Goals: � Investigate Cognitive Radio Strategies & Spectrum Sharing Algorithms � Explore flexible, power efficient wireless architectures � Develop board level platform for system prototyping & subsequent distribution to research community 5
Project Team � WINLAB, Rutgers University � Bryan Ackland � Ivan Seskar � D. Raychaudhuri � Chris Rose � GEDC, Georgia Institute of Technology � Joy Laskar � Stephane Pinel � Wireless Res. Lab., Lucent Bell Laboratories � Tod Sizer � Dragan Samardzija 6
Platform Goals � Design & build cognitive radio platform that is � High performance � HW & SW Programmable � Physical, baseband & network layer adaptable � Support wide range of spectrum sharing scenarios � Leverage today’s high performance off-the-shelf components to build experimental platform with maximum utility & flexibility � Demonstrate architectures and components that will enable low cost, low power, flexible integrated circuit implementations in near future. 7
Spectrum Management: Problem Scope Spectrum Allocation � Dense deployment of Rules wireless devices, both wide- (static) area and short-range Proliferation of multiple � Auction Spectrum radio technologies, e.g. Coordination Server Server INTERNET (dynamic) 802.11a,b,g, UWB, 802.16, (dynamic) 4G, etc. Dynamic frequency provisioning � How should spectrum Short-range allocation rules evolve to infrastructure AP Spectrum Coordination achieve high efficiency? BTS mode network protocols (e.g. WLAN) Available options include: � Agile radios � Etiquette policy (interference avoidance) � Dynamic centralized allocation methods Spectrum � Distributed spectrum Coordination Ad-hoc protocols coordination sensor cluster Short-range ad-hoc net (low-power, (etiquette) high density) Wide-area infrastructure mode network (e.g. 802.16) Collaborative ad-hoc � networks 8
Cognitive Radio: Design Space Unlicensed band + simple coord protocols Ad-hoc, Ad-hoc, Multi-hop Multi-hop Internet Collaboration Internet Collaboration Server-based Server-based Spectrum Spectrum “Cognitive Radio” Etiquette Etiquette Protocol schemes Complexity (degree of Radio-level Radio-level Spectrum coordination) Spectrum Unlicensed Etiquette Unlicensed Etiquette Band Band Protocol with DCA Protocol with DCA (e.g. 802.11x) (e.g. 802.11x) Agile Internet Agile Internet Wideband Spectrum “Open Access” Wideband Spectrum Radios Leasing + smart radios Radios Leasing Reactive Reactive Rate/Power Rate/Power UWB, Control UWB, Control Spread Spread Static Spectrum Static Spectrum Assignment Assignment Hardware Complexity 9
Cognitive Radio: Capabilities � Spectrum scanning & frequency agility � Fast physical layer adaptation & power control to respond to changing local conditions � Flexible baseband & MAC switchable on a packet-by-packet basis (SDR) to provide interoperability with multiple radio technologies � Capable of higher layer spectrum etiquette or negotiation protocols � Simultaneous heterogeneous radio links � Protocol translation & routing to support heterogeneous and/or ad-hoc networks 10
Cognitive Radio Platform Flexible RF Network Processor (MAC+) Flexible RF Flexible Flexible Baseband (SDR) Antenna CR Strategy local drop (host) Flexible RF � Separate sub-systems to simplify functional implementation & modification by students in experimental environment 11
Platform Partitioning Flexible RF A/D/A Network Processor Flexible (MAC+) A/D/A RF Flexible Flexible Baseband (SDR) Antenna CR Strategy (host) Flexible A/D/A RF A/D/A Antenna & RF Board Baseband & Network Processor Board Board (Georgia Tech.) (Rutgers & Lucent) (Rutgers) 12
Agile Tri-band RF Front-end � Tri-band operation: � 700-800 MHz � 2.40-2.48 GHz ISM band � 5.15-5.825 GHz ISM and UN-II bands � 2 Transmit + 2 Receive channels for data + spectrum monitoring receiver � 20 MHz bandwidth on each channel tunable over band � Narrow band selection performed at baseband � 100mW transmit power (variable) per channel � Sensitivity & linearity to meet 802.11a 13
Tri-band Agile Receiver ~ 800 MHz 2.4 GHz 5.2 GHz I I Channel 1 tri-band Q Q antenna 20 MHz BW tri-band SW IF filter RX M To ~ AgileTriband LNA + Low-IF A baseband ~ 800 MHz Agile High Q matching network T ~150 MHz A/D’s 2.4 GHz R I 5.2 GHz x I I Channel 2 SOC Q Q 20 MHz BW tri-band IF filter RX SOP tri-band ~ antenna Tri-band Sensing /Monitoring I Power detection Unit Standard identification Q 20 MHz BW tri-band tri-band IF filter RX VGA 14
Reconfigurable RFIC’s for Compact Intelligent RF Front-end Switched-L Frequency Agile VCO 7 Oscillation Frequency (in GHz) Band-I Band-II 6 5 4 3 2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 Vtune (in V) 15
Tri-band Antennas � Triple-Broadband Antenna for handheld terminals - planar antenna structure - multi-band 5 - broadband 4 VSWR 3 2 1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Frequency (GHz) PCB Frequency Range (MHz): 810-1000 1600-2500 4000-6000 VSWR: ≤ 1.5 Pattern (azimuth plane) : Omni-directional Non-omni Peak Gain (azimuth plane) : 0 dBi 3 dBi Polarization: Mixed Antenna dimensions: 50 mm × 50 mm × 0.2 mm 16
GaTech System-on-Package RF-MEMS Switch Reconfigurable CMOS RFIC RF Tx / Rx Flexible baseband FR-4 Multi- Organic high density multi-layer band/wideband antenna. RF-MEMS Switch & Multi-band Antenna Reconfigurable CMOS RFIC 5 V V D V D D D Vg D 4 V L R D ain b 1 3 O Q R VSWR R C u C 2 3 Q 3 t Q 5 3 1 C C L(active) R 4 1 2 2 C G G G R 2 N N N 1 1 G D D D GN 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 N D D Frequency (GHz) 17
Baseband & Network Processor � Interface to multiple radio channels � Real time spectral analysis � Support comparison of HW & SW baseband solution � MAC, protocol conversion, SAR, routing � Data rates (total) up to 100 Mb/s � Support novel reconfigurable architectures in baseband and network layers � Clean partitions between Baseband, NP and CR � Simple programming environment (not DSP) � Fast reconfiguration time (~ µ s) 18
Bell Labs Programmable Radio Platform Megarray Ethernet XC2V6000 TMS320C6701 Connector- FPGA 244 Configurable I/O pins MPC8260 � 1 GFLOPS TMS320C6701 � 6M gates programmable logic � 280 MIPS MPC8260 � 2.5 Megabits DPRAM in FPGA � 244 configurable I/O pins � 144 dedicated multipliers 19
WINLAB Baseband Platform GV300 2 Virtex™-II FPGAs � (XC2V3000) each with 256K x 18 ZBT SRAMs 1 Spartan™-II FPGA for � External Interface 1 Spartan™-II FPGA for � Configuration Control � USB interface Four 100 MHz 12-bit A/D � and four 100 MHz 12-bit D/A channels On-board 100 MHz � programmable clock oscillator � 32 Bit LVDS interface 2M x 8 configuration � FLASH 20
Baseband & Network Processor Network Data, control & Baseband sensing to/from FPGA SDRAM FPGA RF front-end 64 Virtex-4 (128MB) Virtex-4 94K logic cells 94K logic cells Soft RISC cores 160 DSP slices PowerPC (RTOS) DRAM EEPROM SRAM (64MB) PowerPC (config) (4MB) PowerQuick III 600 MHz (LINUX) Gig-E USB-II 21
Network Processor based on Multiple RISC Cores Packet to/from Buffer (DRAM) baseband Packet Scheduler (RISC) to/from CR Header host Buffer Packet Local Processor I&D (RISC/reconfig) Packet Local Processor I&D (RISC/reconfig) Local Packet I&D Processor (RISC/reconfig) External DRAM 22
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