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Head First into GlobalISel Or: How to delete SelectionDAG in 100* easy commits 1 LLVM Dev Meeting 2017 Justin Bogner, Aditya Nandakumar, Daniel Sanders Apple Porting to GlobalISel What is the structure of a GlobalISel backend? How

  1. Argument Handling void assignValueToReg( unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { switch (VA.getLocInfo()) { default : Extended Assign MIRBuilder.buildCopy(ValVReg, PhysReg); break ; %tmp:_( s64 ) = COPY PhysReg case CCValAssign :: LocInfo ::SExt: case CCValAssign :: LocInfo ::ZExt: case CCValAssign :: LocInfo ::AExt: { auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); MIRBuilder.buildTrunc(ValVReg, Copy); break ; } } MIRBuilder.getMBB().addLiveIn(PhysReg); } 37 GlobalISel Tutorial • LLVM Dev Meeting 2017

  2. Argument Handling void assignValueToReg( unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { switch (VA.getLocInfo()) { default : Extended Assign MIRBuilder.buildCopy(ValVReg, PhysReg); break ; %tmp:_( s64 ) = COPY PhysReg case CCValAssign :: LocInfo ::SExt: case CCValAssign :: LocInfo ::ZExt: %ValVReg:_( s32 ) = G_TRUNC %tmp( s64 ) case CCValAssign :: LocInfo ::AExt: { auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); MIRBuilder.buildTrunc(ValVReg, Copy); break ; } } MIRBuilder.getMBB().addLiveIn(PhysReg); } 38 GlobalISel Tutorial • LLVM Dev Meeting 2017

  3. Argument Handling void assignValueToReg( unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { switch (VA.getLocInfo()) { default : Extended Assign MIRBuilder.buildCopy(ValVReg, PhysReg); break ; %tmp:_( s64 ) = COPY PhysReg case CCValAssign :: LocInfo ::SExt: case CCValAssign :: LocInfo ::ZExt: %ValVReg:_( s32 ) = G_TRUNC %tmp( s64 ) case CCValAssign :: LocInfo ::AExt: { auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); MIRBuilder.buildTrunc(ValVReg, Copy); break ; } } MIRBuilder.getMBB().addLiveIn(PhysReg); } 39 GlobalISel Tutorial • LLVM Dev Meeting 2017

  4. Lower Formal Args bool BPFCallLowering ::lowerFormalArguments( MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef < unsigned > VRegs) { // … SmallVector < ArgInfo , 8> InArgs; unsigned i = 0; for ( auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList ::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); } 40 GlobalISel Tutorial • LLVM Dev Meeting 2017

  5. Lower Formal Args bool BPFCallLowering ::lowerFormalArguments( MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef < unsigned > VRegs) { // … SmallVector < ArgInfo , 8> InArgs; unsigned i = 0; for ( auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList ::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); } 41 GlobalISel Tutorial • LLVM Dev Meeting 2017

  6. Lower Formal Args bool BPFCallLowering ::lowerFormalArguments( MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef < unsigned > VRegs) { // … SmallVector < ArgInfo , 8> InArgs; unsigned i = 0; for ( auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList ::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); } 42 GlobalISel Tutorial • LLVM Dev Meeting 2017

  7. Lower Formal Args bool BPFCallLowering ::lowerFormalArguments( MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef < unsigned > VRegs) { // … SmallVector < ArgInfo , 8> InArgs; unsigned i = 0; for ( auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList ::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); } 43 GlobalISel Tutorial • LLVM Dev Meeting 2017

  8. Lower Formal Args bool BPFCallLowering ::lowerFormalArguments( MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef < unsigned > VRegs) { // … SmallVector < ArgInfo , 8> InArgs; unsigned i = 0; for ( auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList ::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); } 44 GlobalISel Tutorial • LLVM Dev Meeting 2017

  9. Lower Formal Args bool BPFCallLowering ::lowerFormalArguments( MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef < unsigned > VRegs) { // … SmallVector < ArgInfo , 8> InArgs; unsigned i = 0; for ( auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList ::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); } 45 GlobalISel Tutorial • LLVM Dev Meeting 2017

  10. Test Lowering ; CHECK: [[IN:%[0-9]+]]:_( s64 ) = COPY %r1 ; CHECK: RET define void @f( i64 %a) { ret void } llc -global-isel -march=bpf -stop-after=irtranslator 46 GlobalISel Tutorial • LLVM Dev Meeting 2017

  11. Test Lowering ; CHECK: [[CP:%[0-9]+]]:_( s64 ) = COPY %r1 ; CHECK: [[IN:%[0-9]+]]:_( s32 ) = G_TRUNC [[CP]] ; CHECK: RET define void @f( i32 %a) { ret void } llc -global-isel -march=bpf -stop-after=irtranslator 47 GlobalISel Tutorial • LLVM Dev Meeting 2017

  12. Lower Return struct OutgoingHandler : public BPFHandler { OutgoingHandler(…, MachineInstrBuilder &MIB) : BPFHandler(…), MIB(MIB) {} MachineInstrBuilder &MIB; // … }; 48 GlobalISel Tutorial • LLVM Dev Meeting 2017

  13. Lower Return void assignValueToReg( unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { unsigned ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState ::Implicit); } 49 GlobalISel Tutorial • LLVM Dev Meeting 2017

  14. Lower Return void assignValueToReg( unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { unsigned ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState ::Implicit); } 50 GlobalISel Tutorial • LLVM Dev Meeting 2017

  15. Lower Return void assignValueToReg( unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { unsigned ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState ::Implicit); } 51 GlobalISel Tutorial • LLVM Dev Meeting 2017

  16. Lower Return void assignValueToReg( unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { unsigned ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState ::Implicit); } 52 GlobalISel Tutorial • LLVM Dev Meeting 2017

  17. Lower Return bool BPFCallLowering ::lowerReturn( MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { auto MIB = MIRBuilder.buildInstrNoInsert( BPF ::RET); bool Success = true ; if (VReg) { // … ArgInfo OrigArg{VReg, Val->getType()}; setArgFlags(OrigArg, AttributeList ::ReturnIndex, DL, F); OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; } 53 GlobalISel Tutorial • LLVM Dev Meeting 2017

  18. Lower Return bool BPFCallLowering ::lowerReturn( MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { %0:_(s64) = COPY %r1 auto MIB = MIRBuilder.buildInstrNoInsert( BPF ::RET); …G_ADD… bool Success = true ; … if (VReg) { // … InsertPt ArgInfo OrigArg{VReg, Val->getType()}; setArgFlags(OrigArg, AttributeList ::ReturnIndex, DL, F); RET OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; } 54 GlobalISel Tutorial • LLVM Dev Meeting 2017

  19. Lower Return bool BPFCallLowering ::lowerReturn( MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { %0:_(s64) = COPY %r1 auto MIB = MIRBuilder.buildInstrNoInsert( BPF ::RET); …G_ADD… bool Success = true ; … if (VReg) { // … InsertPt ArgInfo OrigArg{VReg, Val->getType()}; setArgFlags(OrigArg, AttributeList ::ReturnIndex, DL, F); RET OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; } 55 GlobalISel Tutorial • LLVM Dev Meeting 2017

  20. Lower Return bool BPFCallLowering ::lowerReturn( MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { %0:_(s64) = COPY %r1 auto MIB = MIRBuilder.buildInstrNoInsert( BPF ::RET); …G_ADD… bool Success = true ; … if (VReg) { // … %r0 = COPY %VReg ArgInfo OrigArg{VReg, Val->getType()}; InsertPt setArgFlags(OrigArg, AttributeList ::ReturnIndex, DL, F); RET implicit %r0 OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; } 56 GlobalISel Tutorial • LLVM Dev Meeting 2017

  21. Lower Return bool BPFCallLowering ::lowerReturn( MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { %0:_(s64) = COPY %r1 auto MIB = MIRBuilder.buildInstrNoInsert( BPF ::RET); …G_ADD… bool Success = true ; … if (VReg) { // … %1:_(s64) = G_ANYEXT %VReg %r0 = COPY %1 ArgInfo OrigArg{VReg, Val->getType()}; InsertPt setArgFlags(OrigArg, AttributeList ::ReturnIndex, DL, F); RET implicit %r0 OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; } 57 GlobalISel Tutorial • LLVM Dev Meeting 2017

  22. Lower Return bool BPFCallLowering ::lowerReturn( MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { %0:_(s64) = COPY %r1 auto MIB = MIRBuilder.buildInstrNoInsert( BPF ::RET); …G_ADD… bool Success = true ; … if (VReg) { // … %1:_(s64) = G_ANYEXT %VReg %r0 = COPY %1 ArgInfo OrigArg{VReg, Val->getType()}; BPF::RET implicit %r0 setArgFlags(OrigArg, AttributeList ::ReturnIndex, DL, F); InsertPt OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; } 58 GlobalISel Tutorial • LLVM Dev Meeting 2017

  23. Test ArgLowering ; CHECK: [[IN:%[0-9]+]]:_( s64 ) = COPY %r1 ; CHECK: %r0 = COPY [[IN]] ; CHECK: RET implicit %r0 define i64 @f( i64 %a) { ret i64 %a } llc -global-isel -march=bpf -stop-after=irtranslator 59 GlobalISel Tutorial • LLVM Dev Meeting 2017

  24. Test ArgLowering ; CHECK: [[TMP:%[0-9]+]]:_( s64 ) = COPY %r1 ; CHECK: [[IN:%[0-9]+]]:_( s32 ) = G_TRUNC [[TMP]] ; CHECK: [[EXT:%[0-9]+]]:_( s64 ) = G_ANYEXT [[IN]] ; CHECK: %r0 = COPY [[EXT]] define i32 @f( i32 %a) { ret i32 %a } llc -global-isel -march=bpf -stop-after=irtranslator 60 GlobalISel Tutorial • LLVM Dev Meeting 2017

  25. Register Banks Wiring up GISel TargetMachine/SubTarget irtranslator CallLowering RegBankInfo regbankselect legalizer LegalizerInfo instruction-select InstructionSelector 61 GlobalISel Tutorial • LLVM Dev Meeting 2017

  26. Register Banks • Group register classes, ignoring size and type • Di ff erent banks imply transferring values is costly • A typical split is general purpose vs floating point 62 GlobalISel Tutorial • LLVM Dev Meeting 2017

  27. Define Register Banks def AnyGPRRegBank : RegisterBank <"AnyGPR", [ GPR ]>; Define a bank for BPF's GPRs in BPFRegisterBanks.td 63 GlobalISel Tutorial • LLVM Dev Meeting 2017

  28. More Register Classes GPR32all GPR32 FPR8 DDD GPR32sp FPR16 FPR32 GPR64sp FPR128 DD DDDD GPR64sponly GPR32sponly GPR64common CCR tcGPR64 GPR64 GPR32common QQQ GPR64all QQQQ QQ FPR64 AArch64 is a good example with more register classes 64 GlobalISel Tutorial • LLVM Dev Meeting 2017

  29. AArch64 Register Banks GPR FPR CC GPR32 FPR8 CCR GPR32sp FPR16 GPR32common FPR32 GPR32sponly FPR64 GPR32all FPR128 GPR64 DD GPR64sp DDD GPR64common DDDD GPR64sponly QQ GPR64all QQQ tcGPR64 QQQQ 65 GlobalISel Tutorial • LLVM Dev Meeting 2017

  30. AArch64 Register Banks /// General Purpose Registers : W , X . def GPRRegBank : RegisterBank <"GPR", [ GPR64all ]>; /// Floating Point / Vector Registers : B , H , S , D , Q . def FPRRegBank : RegisterBank <"FPR", [ QQQQ ]>; /// Conditional register: NZCV . def CCRegBank : RegisterBank <"CC", [ CCR ]>; We only need to specify the largest register class to define each bank 66 GlobalISel Tutorial • LLVM Dev Meeting 2017

  31. Generated Bank Info class BPFGenRegisterBankInfo : public RegisterBankInfo { protected : #define GET_TARGET_REGBANK_CLASS #include "BPFGenRegisterBank.inc" }; 67 GlobalISel Tutorial • LLVM Dev Meeting 2017

  32. Register Bank Mapping BPFRegisterBankInfo : BPFGenRegisterBankInfo getRegBankFromRegClass(...) getInstrMapping(...) getInstrAlternativeMappings(...) 68 GlobalISel Tutorial • LLVM Dev Meeting 2017

  33. Register Bank Mapping BPFRegisterBankInfo : BPFGenRegisterBankInfo getRegBankFromRegClass(...) getInstrMapping(...) getInstrAlternativeMappings(...) Given a register class, return the register bank 69 GlobalISel Tutorial • LLVM Dev Meeting 2017

  34. Register Bank Mapping BPFRegisterBankInfo : BPFGenRegisterBankInfo getRegBankFromRegClass(...) getInstrMapping(...) getInstrAlternativeMappings(...) 70 GlobalISel Tutorial • LLVM Dev Meeting 2017

  35. getInstrMapping const auto &Mapping = getInstrMappingImpl(MI); if (Mapping.isValid()) return Mapping; Leverage getInstrMappingImpl to handle generic instructions 71 GlobalISel Tutorial • LLVM Dev Meeting 2017

  36. getInstrMapping SmallVector < const ValueMapping *, 8> ValMappings(NumOperands); for ( unsigned Idx = 0; Idx < NumOperands; ++Idx) { if (MI.getOperand(Idx).isReg()) { LLT Ty = MRI.getType(MI.getOperand(Idx).getReg()); auto Size = Ty.getSizeInBits(); ValMappings[Idx] = &getValueMapping(0, Size, BPF ::AnyGPRRegBank); } } Map each operand to an appropriate bank for target instructions 72 GlobalISel Tutorial • LLVM Dev Meeting 2017

  37. Test Bank Selection ; CHECK-LABEL: name: defaultMapping ; CHECK: %[[CP:[0-9]+]]:anygpr( s64 ) = COPY %r1 ; CHECK: %[[ADD:[0-9]+]]:anygpr( s64 ) = G_ADD %[[CP]], %[[CP]] %0:_( s64 ) = COPY %r1 %1:_( s64 ) = G_ADD %0, %0 llc -march=bpf -global-isel -run-pass=regbankselect 73 GlobalISel Tutorial • LLVM Dev Meeting 2017

  38. getInstrAlternativeMappings case TargetOpcode ::G_OR: { InstructionMappings AltMappings; AltMappings.push_back(getInstructionMapping( /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size), /*NumOperands*/ 3)); AltMappings.push_back(getInstructionMapping( /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size), /*NumOperands*/ 3)); return AltMappings; } In AArch64, 32 and 64-bit " or " map equally well on FPR or GPR 74 GlobalISel Tutorial • LLVM Dev Meeting 2017

  39. getInstrAlternativeMappings case TargetOpcode ::G_OR: { InstructionMappings AltMappings; AltMappings.push_back(getInstructionMapping( /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size), /*NumOperands*/ 3)); AltMappings.push_back(getInstructionMapping( /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size), /*NumOperands*/ 3)); return AltMappings; } In AArch64, 32 and 64-bit " or " map equally well on FPR or GPR 75 GlobalISel Tutorial • LLVM Dev Meeting 2017

  40. getInstrAlternativeMappings case TargetOpcode ::G_OR: { InstructionMappings AltMappings; AltMappings.push_back(getInstructionMapping( /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size), /*NumOperands*/ 3)); AltMappings.push_back(getInstructionMapping( /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size), /*NumOperands*/ 3)); return AltMappings; } In AArch64, 32 and 64-bit " or " map equally well on FPR or GPR 76 GlobalISel Tutorial • LLVM Dev Meeting 2017

  41. Legalizer Wiring up GISel TargetMachine/SubTarget irtranslator CallLowering RegBankInfo regbankselect legalizer LegalizerInfo instruction-select InstructionSelector 77 GlobalISel Tutorial • LLVM Dev Meeting 2017

  42. Legalizer • Transform gMIR into legal instructions • Legal is defined as • Selectable by target • Operating on vregs that can be loaded/stored • No SelectionDAG like type legalization 78 GlobalISel Tutorial • LLVM Dev Meeting 2017

  43. Legalization Pass Drives Legalization Specifies Legality Uses Legalizer LegalizerInfo Uses LegalizerHelper Helpers for Common Operations 79 GlobalISel Tutorial • LLVM Dev Meeting 2017

  44. Legality Specifiers setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction) 80 GlobalISel Tutorial • LLVM Dev Meeting 2017

  45. Legality Specifiers setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction) %2:_( s64 ) = G_ADD %0, %1 setAction({G_ADD, s64 }, Legal); // Want 64 bit Dest 
 %3:_( s32 ) = … setAction({G_ADD, s32 }, WidenScalar); %4:_( s32 ) = G_ADD %3, %3 81 GlobalISel Tutorial • LLVM Dev Meeting 2017

  46. Legality Specifiers setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction) %2:_( s64 ) = G_ADD %0, %1 setAction({G_ADD, s64 }, Legal); // Want 64 bit Dest 
 %3:_( s32 ) = … setAction({G_ADD, s32 }, WidenScalar); %4:_( s32 ) = G_ADD %3, %3 82 GlobalISel Tutorial • LLVM Dev Meeting 2017

  47. Legality Specifiers setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction) %2:_( s64 ) = G_ADD %0, %1 setAction({G_ADD, s64 }, Legal); // Want 64 bit Dest %3:_( s32 ) = … setAction({G_ADD, s32 }, WidenScalar); %5:_( s64 ) = G_ANYEXT %3(s32) %6:_( s64 ) = G_ADD %5, %5 83 GlobalISel Tutorial • LLVM Dev Meeting 2017

  48. Legality Specifiers setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction) %2:_( s64 ) = G_ADD %0, %1 setAction({G_ANYEXT, 0, s64 }, Legal); %3:_( s32 ) = … setAction({G_ANYEXT, 1, s32 }, Legal); %5:_( s64 ) = G_ANYEXT %3(s32) %6:_( s64 ) = G_ADD %5, %5 84 GlobalISel Tutorial • LLVM Dev Meeting 2017

  49. Legalization in BPF • Set LegalizerAction in the constructor. • Implement legalizeCustom for custom hook if required. 85 GlobalISel Tutorial • LLVM Dev Meeting 2017

  50. BPFLegalizerInfo BPFLegalizerInfo ::BPFLegalizerInfo() { using namespace TargetOpcode ; const LLT p0 = LLT ::pointer(0, 64); // … const LLT s32 = LLT ::scalar(32); const LLT s64 = LLT ::scalar(64); for ( auto Ty : { p0 , s1 , s8 , s16 , s32 , s64 }) setAction({G_IMPLICIT_DEF, Ty }, Legal); setAction({G_PHI, s64 }, Legal); for ( auto Ty : { s1 , s8 , s16 , s32 }) setAction({G_PHI, Ty }, WidenScalar); // … computeTables(); } 86 GlobalISel Tutorial • LLVM Dev Meeting 2017

  51. BPFLegalizerInfo BPFLegalizerInfo ::BPFLegalizerInfo() { using namespace TargetOpcode ; const LLT p0 = LLT ::pointer(0, 64); // … const LLT s32 = LLT ::scalar(32); const LLT s64 = LLT ::scalar(64); for ( auto Ty : { p0 , s1 , s8 , s16 , s32 , s64 }) setAction({G_IMPLICIT_DEF, Ty }, Legal); setAction({G_PHI, s64 }, Legal); for ( auto Ty : { s1 , s8 , s16 , s32 }) setAction({G_PHI, Ty }, WidenScalar); // … computeTables(); } 87 GlobalISel Tutorial • LLVM Dev Meeting 2017

  52. BPFLegalizerInfo BPFLegalizerInfo ::BPFLegalizerInfo() { using namespace TargetOpcode ; const LLT p0 = LLT ::pointer(0, 64); // … const LLT s32 = LLT ::scalar(32); const LLT s64 = LLT ::scalar(64); for ( auto Ty : { p0 , s1 , s8 , s16 , s32 , s64 }) setAction({G_IMPLICIT_DEF, Ty }, Legal); setAction({G_PHI, s64 }, Legal); for ( auto Ty : { s1 , s8 , s16 , s32 }) setAction({G_PHI, Ty }, WidenScalar); // … computeTables(); } 88 GlobalISel Tutorial • LLVM Dev Meeting 2017

  53. BPFLegalizerInfo BPFLegalizerInfo ::BPFLegalizerInfo() { using namespace TargetOpcode ; const LLT p0 = LLT ::pointer(0, 64); // … const LLT s32 = LLT ::scalar(32); const LLT s64 = LLT ::scalar(64); for ( auto Ty : { p0 , s1 , s8 , s16 , s32 , s64 }) setAction({G_IMPLICIT_DEF, Ty }, Legal); setAction({G_PHI, s64 }, Legal); for ( auto Ty : { s1 , s8 , s16 , s32 }) setAction({G_PHI, Ty }, WidenScalar); // … computeTables(); } 89 GlobalISel Tutorial • LLVM Dev Meeting 2017

  54. BPFLegalizerInfo BPFLegalizerInfo ::BPFLegalizerInfo() { using namespace TargetOpcode ; const LLT p0 = LLT ::pointer(0, 64); // … const LLT s32 = LLT ::scalar(32); const LLT s64 = LLT ::scalar(64); for ( auto Ty : { p0 , s1 , s8 , s16 , s32 , s64 }) setAction({G_IMPLICIT_DEF, Ty }, Legal); setAction({G_PHI, s64 }, Legal); for ( auto Ty : { s1 , s8 , s16 , s32 }) setAction({G_PHI, Ty }, WidenScalar); // … computeTables(); } 90 GlobalISel Tutorial • LLVM Dev Meeting 2017

  55. Test Legalizer ; CHECK: [[IN:%[0-9]+]]:_( s64 ) = COPY %r1 ; CHECK: %r0 = COPY [[IN]] ; CHECK: RET implicit %r0 %0:_( s64 ) = COPY %r1 %r0 = COPY %0( s64 ) RET implicit %r0 llc -march=bpf -global-isel -run-pass=legalizer 91 GlobalISel Tutorial • LLVM Dev Meeting 2017

  56. Test Legalizer %0:_( s64 ) = COPY %r1 %1:_( s64 ) = G_ADD %0, %0 %r0 = COPY %1( s64 ) RET implicit %r0 LLVM ERROR: unable to legalize instruction 92 GlobalISel Tutorial • LLVM Dev Meeting 2017

  57. BPFLegalizerInfo setAction({G_ADD, s64 }, Legal); for ( const auto &Ty : { s1 , s8 , s16 , s32 }) setAction({G_ADD, Ty }, WidenScalar); 93 GlobalISel Tutorial • LLVM Dev Meeting 2017

  58. BPFLegalizerInfo setAction({G_ADD, s64 }, Legal); for ( const auto &Ty : { s1 , s8 , s16 , s32 }) setAction({G_ADD, Ty }, WidenScalar); 94 GlobalISel Tutorial • LLVM Dev Meeting 2017

  59. Test Legalizer ; CHECK: [[ADD:%[0-9]+]]:_( s64 ) = G_ADD %0:_( s64 ) = COPY %r1 %1:_( s64 ) = G_ADD %0, %0 %r0 = COPY %1( s64 ) RET implicit %r0 95 GlobalISel Tutorial • LLVM Dev Meeting 2017

  60. Test Legalizer ; CHECK: [[ADD:%[0-9]+]]:_( s64 ) = G_ADD %0:_( s64 ) = COPY %r1 %1:_( s32 ) = G_TRUNC %0 %2:_( s32 ) = G_ADD %1, %1 ; ... 96 GlobalISel Tutorial • LLVM Dev Meeting 2017

  61. Custom Legalization • Implement legalizeCustom method • Specify LegalizationAction as Custom • Legalize G_SELECT into pseudo instruction (BPF_SELECT_CC) 97 GlobalISel Tutorial • LLVM Dev Meeting 2017

  62. Custom Legalization %2:_( s64 ) = G_ICMP <pred>, %0( s64 ), %1( s64 ) %3:_( s1 ) = G_TRUNC %2( s64 ) %4:_( s64 ) = G_SELECT %3( s1 ), %5( s64 ), %6 %4:_( s64 ) = BPF_SELECT_CC %0, %1, <pred>, %5, %6 98 GlobalISel Tutorial • LLVM Dev Meeting 2017

  63. Custom Legalization %2:_( s64 ) = G_ICMP <pred>, %0( s64 ), %1( s64 ) %3:_( s1 ) = G_TRUNC %2( s64 ) %4:_( s64 ) = G_SELECT %3( s1 ), %5( s64 ), %6 %4:_( s64 ) = BPF_SELECT_CC %0, %1, <pred>, %5, %6 99 GlobalISel Tutorial • LLVM Dev Meeting 2017

  64. Custom Legalization def BPF_SELECT_CC : Pseudo <(outs type1: $dst), (ins type0: $lhs, type0: $rhs, i64imm: $cc, type1: $true, type1: $false), “BPF_SELECT_CC\t$dst, $lhs, $rhs, $cc, $true, $false", []>; 100 GlobalISel Tutorial • LLVM Dev Meeting 2017

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