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Generic Polyphase Filterbanks with CUDA Jan Krmer DLR German - PowerPoint PPT Presentation

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Generic Polyphase Filterbanks with CUDA Jan Krmer DLR German Aerospace Center Communication and Navigation Satellite Networks Weling 04.02.2017 r rr www.dlr.de Slide 1 of

  1. Generic Polyphase Filterbanks with CUDA Jan Krämer DLR German Aerospace Center Communication and Navigation Satellite Networks Weßling 04.02.2017 ❑♥♦✇❧❡❞❣❡ ❢♦r ❚♦♠♦rr♦✇ ❉▲❘

  2. www.dlr.de · Slide 1 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Outline 1. Motivation 2. Short introduction to CUDA 3. PFBs and the Channelizer 4. Translation to CUDA 5. Results 6. Release plans and future changes ❉▲❘

  3. www.dlr.de · Slide 1 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Outline 1. Motivation 2. Short introduction to CUDA 3. PFBs and the Channelizer 4. Translation to CUDA 5. Results 6. Release plans and future changes ❉▲❘

  4. www.dlr.de · Slide 2 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Once upon a time in a space project Multicarrier scheme with 15/30/45 carrier ❉▲❘

  5. www.dlr.de · Slide 2 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Once upon a time in a space project Multicarrier scheme with 15/30/45 carrier So let’s just use a PFB, right? ❉▲❘

  6. www.dlr.de · Slide 3 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Early Trouble 45 carrier means 45x the bandwidth Only 12-15 % guardband available At least 3x oversampling needed Up to 1500 tap filters needed ❉▲❘

  7. www.dlr.de · Slide 3 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Early Trouble 45 carrier means 45x the bandwidth Only 12-15 % guardband available At least 3x oversampling needed Up to 1500 tap filters needed ❉▲❘

  8. www.dlr.de · Slide 4 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Early Trouble CPU reference implementation 1000 taps 35dB rejection Originally 9x oversampling 2 Msamples/second achieved ⇒ 4 Msamples/second needed ❉▲❘

  9. www.dlr.de · Slide 4 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Outline 1. Motivation 2. Short introduction to CUDA 3. PFBs and the Channelizer 4. Translation to CUDA 5. Results 6. Release plans and future changes ❉▲❘

  10. www.dlr.de · Slide 5 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 What is CUDA NVidias framework for GPGPU Used mainly to accelerate scientific computing Uses the massive amount of available compute cores inside a GPU ❉▲❘

  11. www.dlr.de · Slide 6 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 GPU Interior GPU consists of several Streaming Multiprocessors (SM) Each SM consists of numerous compute or CUDA cores Single-Instruction Multiple-Threads (SIMT) structure Several kinds of memory Global Memory (GDDR5 RAM) (slow) On-Chip (shared) Memory per SM (faster) Registers (blazingly fast) ❉▲❘

  12. www.dlr.de · Slide 7 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 CUDA Interior Builds a (up to) 3 dimensional Grid The Gid contains the (up to) 3 dimensional Thread Blocks containing the threads Groups of 32 threads inside a Thread Block are grouped together ⇒ Warp ❉▲❘

  13. www.dlr.de · Slide 8 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 CUDA Interior ❉▲❘

  14. www.dlr.de · Slide 9 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Thread Execution Each Block has a unique ID inside the Grid ⇒ Each thread has a unique global ID Thread Scheduler assigns each Thread Block to one SM and executed concurrently All threads in a Warp are executed concurrently inside the SM ❉▲❘

  15. www.dlr.de · Slide 10 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Performance Bottlenecks Uncoalesced loads from global memory ⇒ Several cache-lines to be loaded ❉▲❘

  16. www.dlr.de · Slide 10 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Performance Bottlenecks Uncoalesced loads from global memory ⇒ Several cache-lines to be loaded Bank conflicts when accessing shared memory ❉▲❘

  17. www.dlr.de · Slide 10 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Performance Bottlenecks Uncoalesced loads from global memory ⇒ Several cache-lines to be loaded Bank conflicts when accessing shared memory Branching ⇒ Which instruction should be executed? ❉▲❘

  18. www.dlr.de · Slide 10 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Outline 1. Motivation 2. Short introduction to CUDA 3. PFBs and the Channelizer 4. Translation to CUDA 5. Results 6. Release plans and future changes ❉▲❘

  19. www.dlr.de · Slide 11 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Why PFBs and Channelizers/Synthesizers? Used to reduce computational complexity for resampling filters Used to separate small bandwidth channels Used to generate multicarrier ’broadband’ signals ❉▲❘

  20. www.dlr.de · Slide 12 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Structure of a PFB Channelizer Extracting a channel with 1 N of the total bandwidth Mix Signal to Baseband Apply anti-alias filter Downsample the signal ❉▲❘

  21. www.dlr.de · Slide 13 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Structure of a PFB Channelizer Extracting a channel with 1 N of the total bandwidth Mix Signal to Baseband Apply anti-alias filter Downsample the signal N -phase PFB splits one-dimensional filter in its N different phase shares ❉▲❘

  22. www.dlr.de · Slide 14 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Structure of a PFB Channelizer Taps of the regular prototype filter ❉▲❘

  23. www.dlr.de · Slide 15 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Structure of a PFB Channelizer Taps of the regular prototype filter Split into 4 polyphase partitions ❉▲❘

  24. www.dlr.de · Slide 16 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Structure of a PFB Channelizer Taps of the regular prototype filter Split into 4 polyphase partitions Newly structured dataflow ❉▲❘

  25. www.dlr.de · Slide 17 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Structure of a PFB Channelizer Taps of the regular prototype filter Split into 4 polyphase partitions Newly structured dataflow FFT separates all the channels ❉▲❘

  26. www.dlr.de · Slide 18 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Structure of a PFB Channelizer Oversampling can be achieved by manipulating the input commutator and FFT input To synthesize several incoming channels just the reorder the operations ❉▲❘

  27. www.dlr.de · Slide 18 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Outline 1. Motivation 2. Short introduction to CUDA 3. PFBs and the Channelizer 4. Translation to CUDA 5. Results 6. Release plans and future changes ❉▲❘

  28. www.dlr.de · Slide 18 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 ❉▲❘

  29. www.dlr.de · Slide 19 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Identifying necessary operations Channelizer consists of 4 operations Shuffle the input stream Polyphase filtering FFT Shuffle the output stream ❉▲❘

  30. www.dlr.de · Slide 20 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Input Shuffling Input Commutator implemented as matrix traversal Number of threads needs to accomodate to the filter history ⇒ Grid dimension takes care of this Input buffer reads are coalesced ⇒ Block x-dimension same size as polyphase partition Intermediate buffer writes are therfore not coalesced ❉▲❘

  31. www.dlr.de · Slide 21 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Filter Operations Block X dimension computes several input samples Block Y dimension computes oversampled output samples Grid X dimension represents polyphase partitions Grid Y dimension provide additional concurrency (due to block thread limits) ❉▲❘

  32. www.dlr.de · Slide 22 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Filter Operations Each threadblock transfers memory from global memory to shared memory Each sample is accessed several times ⇒ shared memory offers faster memory transfers Register and shared memory spills are avoided ❉▲❘

  33. www.dlr.de · Slide 23 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 FFT and Output Shuffling FFT is the CuFFT of CUDA Output shuffling implemented as double loop done on Host CPU (for now) ❉▲❘

  34. www.dlr.de · Slide 23 of 27 > Generic Polyphase Filterbanks with CUDA > Jan Krämer > 04.02.2017 Outline 1. Motivation 2. Short introduction to CUDA 3. PFBs and the Channelizer 4. Translation to CUDA 5. Results 6. Release plans and future changes ❉▲❘

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