Front-End Electronics based on Waveform Sampling Feature Extraction Grzegorz Pastuszak and Marcin Ziembicki Warsaw University of Technology and AstroCeNT Advanced Workshop on Modern FPGA Based Technology for Scientific Computing ICTP, Trieste, 2019-05-22
Introduction HV for 20” PMTs Benefits of Waveform Sampling Frontend board Hyper-Kamiokande case Voltage (generally applicable) PMT base multiplier Other FE EMI pickup EMI pickup (HV supply) modules Cherenkov Shaper Anti- photons (Low Pass Filter) Aliasing PMT (Low Pass Filter) Power Voltage Interconnects Interconnects supplies multiplier ADC ADC (HV supply) DAQ = noise source FPGA HV for 3” PMTs (signal processing) = EMI (deterministic source) • Possibility to implement completely dead-time free system. • Ability to disentangle overlapping pulses (pile-up) • Can subtract off periodic EMI by digital filters implemented in FPGA firmware. • There is a price to pay: power consumption, cost, data rate . – Can we reduce the above without affecting the physics performance? 2
Fast Digitizer at Reasonable Power & Cost Switched Capacitor Arrays (DRS4 example) Only short sampling digitization segments are sampling digitization interesting, so … lost events Sensor INTRODUCTION OF DEAD TIME → Not a problem if mean inter-pulse period is large fast sampling → SCA compared to the dead time Avoiding dead time in capacitor arrays: slow sampling → ADC • Use multiple arrays for single waveform • Use chip with segmented memory (if available) 3
Study of Sampling Systems High resolution Low resolution How poor can the system specs be to still be able to tell when How poor can the picture be to still be able to tell where and how big the pulse was with satisfactory precision ? and how big the tree is with satisfactory precision ? 0.06 0.3 0.15 Short pulse Pulse area = const Wide pulse 0.04 0.2 0.1 High amplitude Small 0.02 0.1 0.05 amplitude 0 0 0 0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60 Time [s] Time [s] Time [s] High bandwidth Low bandwidth 4
Optimizing Signal Chain Voltage multiplier Other FE EMI pickup EMI pickup (HV supply) modules Cherenkov Shaper Anti- photons (Low Pass Filter) Aliasing PMT (Low Pass Filter) Power Voltage Interconnects Interconnects supplies multiplier ADC ADC (HV supply) DAQ = noise source FPGA (signal processing) = EMI (deterministic source) QUESTIONS: • Type and cutoff frequency of analog shaper/anti-aliasing filter? • Speed and resolution of the ADC? • Signal processing methods and sharing of signal processing between FPGA and DAQ • Optimization of resource usage within the FPGA • Quality of time & charge estimates • Two independent compression methods: – Waveform (potentially lossy) – Time/charge (lossless) • Disentanglement of pulse pile-up Need decent model of the full signal chain → having one allows exploration of various variants of shaper/ADC combinations without the need for building prototypes (thus saves labor time) 5
Interactions Buffer size, link bandwidth and storage requirements Compression algorithms Pile-up Processing resolution speed and maximum Data rate pulse rate Dynamic ADC range resolution Pulse width ADC Speed Shaper / anti- System Signal to Time aliasing Filter bandwidth Noise Ratio resolution Noise Charge Signal spectrum resolution processing algorithms FPGA resource usage 6
Timing Resolution of Sampling Digitizers Agilent 33600A (1 GSPS/80 MHz) PURPOSE OF THE STUDY: Determine how fast and how precise does a system needs to be to achieve given performance specs? • Use AWG instead of PMT. AWG • Use large reference pulse (timing ref. sig. accuracy 10 ps) and small, shaped signal pulse (1 mV Custom shapers 100 mV). Shaper • Apply signal processing methods and calculate time difference Δt between ref. and sig. channels. • Repeat multiple times and compute ADC RMS of Δt values. Commercial ADCs (CAEN) • Two shapers: V1720 (250 MSPS/12b) DT5724 – 15 ns and 30 ns rise time (100 MSPS/14b) (10% to 90%), 5-th order Bessel-type low-pass filters. V1730 (500 MSPS/14b) • Shared project WUT/TRIUMF 7 7
Signal Processing Methods Digital Constant Fraction Discriminator: Simple processing → needs little • FPGA resources 3 4 • Does not make any assumption as to the pulse shape 7 6 • Favors high sampling rate, but 6 threshold some improvements are 1 possible for low sampling rates if pulse shape is invariant 2 5 • Poor performance in low SNR conditions - actual sub-sample shift P Time errors and 𝑄 possible correction 𝐷𝑆 = Q 𝑄 − 𝑅 8
Signal Processing – FIR DPLMS Zero DC gain – no baseline estimation needed Signal for timing How to get the filter? What shape? FIR Filter Sampled signal (timing) Time from Position and zero crossing size of the Zero DC gain – no baseline template? Signal for charge estimation estimation needed FIR Filter What shape? Tested response types: (charge) N LEN How to get N linear Charge from the filter? amplitude 1 Gauss + linear 0.5 … or simply subtract pedestal and integrate. A linear 0 • FIR = Finite Impulse Response -0.5 ‘Black - box’ approach → transform known • -1 input into desired output, don’t care how. 2 4 6 8 10 12 N non-zero • Arbitrary filter characteristic possible. 1 Filter should be ‘optimal’ → minimize • Cosine + linear 0.5 certain cost function (constrained 0 optimization) . -0.5 Gatti E., et al., “ Digital Penalized LMS method for filter synthesis with arbitrary constraints and noise ”, NIM A523, 167 -185, 2004 -1 9 2 4 6 8 10 12
Synthesizing FIR filter – Method 1 Digital Penalized LMS Method Input Output Filter Take multiple measurements, then: noiseless signal stationary Minimize overall variance of the response: input signal (our template) noise Sought filter 𝑊𝑏𝑠 𝑧 = 𝒊 1,𝑂 ∙ 𝑺 𝑂,𝑂 ∙ 𝒊 𝑂,1 𝑦 𝑜 = 𝑦 ′ 𝑜 + 𝑦"[𝑜] impulse response Noise auto-covariance matrix number of filter taps of the filter Minimize difference between filter Filter is linear , so the output signal is: response and our desired response 𝑂−1 𝑂−1 2 = 𝒊 1,𝑂 ∙ 𝒚 ′ 𝑙 𝑂,1 − 𝑤 𝑙 2 ℎ 𝑚 ∙ 𝑦 ′ 𝑜 − 𝑚 + 𝐹(𝑧 𝑙 − 𝑤 𝑙 ) 𝑧 𝑜 = ℎ[𝑚] ∙ 𝑦"[𝑜 − 𝑚] 𝑚=0 𝑚=0 Value of k-th N past samples of x’, Therefore, we can deal with noise and sample of the starting from k signal components separately response to x’ Gatti E., et al., “ Digital Penalized LMS method for filter synthesis with 10 arbitrary constraints and noise ”, NIM A523, 167 -185, 2004
Synthesizing FIR filter – Method 1 (cont.) Digital Penalized LMS Method Add additional constraints for frequency response, including gain at DC ... Add constraints related to bit-gain (i.e. how well we are supposed to reject quantization noise) … Finally, build the error functional and minimize it: 𝐵𝑠𝑓𝑏 𝐺𝐽𝑆 = 𝐵𝑠𝑓𝑏(𝑧) 𝐵𝑠𝑓𝑏(𝑦) All components are square functions, so there exists a global minimum – just need → → → to properly choose N , v , , , and → papers don’t say much about that 11
Signal Processing - FIR Filters • Trigger on matched filter response (red) • Use adaptive threshold to prevent false positives (dotted black line) – Average signal to get the threshold and delay FIR Method assumes that processing to check for pulses and their timing shape is constant • Get time using the ‘timing’ filter (blue) • Need on-line Quality Factor to judge Apply correction to counteract non-linear accuracy of estimation shape of the waveform near zero-crossing. 12
Signal Processing – Continued Matched FIR Filter and Cross-Correlation Processing: • Much more complex processing Misaligned pulses – Works well with filter orders of 9-12 Pulses Cross-correlation • Assumes that shape is constant • Similar timing performance to zero- average FIR filter • Relatively easy to disentangle piled-up pulses Aligned pulses Pulses Cross-correlation Sub-sample shifts done using windowed sinc interpolation (Blackman window). FFT interpolation also possible if shifting impulse response. 13
System Model (each channel) Used 250 MHz data to 𝜏 𝑠𝑓𝑔 2 + 𝜏 𝑡𝑗 2 𝜏 𝑔𝑗𝑜𝑏𝑚 = determine actual AWG f S sqrt(noise periodogram) -1 Fit f S = 205.5 MHz * White noise Digital CFD Semi-analog simulation, T S =1 ps - Anti-aliasing FIR + AWG pulse Shaper Sampling Error filter zero-cross TF TF Waveform samples: Analog bandwidth of AWG CR differentiator. Not used for reference channels. T. Lindner/M. Walters is 80 MHz. Depends on ADC. 2 real poles for DT5724 Not needed for V1720 5-th order Bessel filter and FIR Random matched sub-sample shift All transfer functions ( TF ) calculated in s-domain, then used -1 to calculate impulse response. 14
Signal Models 100 MHz, 250 MHz, CH1 = ref, CH2 = ref CH1 = ref, CH2 = ref f 3dB = 26.62 MHz f 3dB = 26.55 MHz filter No anti-aliasing filter No anti-aliasing 2 real poles 2 real poles 250 MHz, CH1 = ref, CH2 = sig (15 ns low power) CH1 = ref, CH2 = sig (15 ns) All pulses matched by FWHM Interpolation artefacts 15
Recommend
More recommend
