Floorplan and Power/ Ground Network Co-Synthesis for Fast Design - PowerPoint PPT Presentation

Floorplan and Power/ Ground Network Co-Synthesis for Fast Design Convergence Chen-Wei Liu 12 and Yao-Wen Chang 2 1 Synopsys Taiwan Limited 2 Department of Electrical Engineering National Taiwan University, Taipei Taiwan April 11, 2006 1

Outline ․ Introduction ․ Proposed Design Flow ․ Floorplan and P/G Network Co-Synthesis Algorithm ․ Experimental Results 2

Outline ․ Introduction ․ Introduction ․ Proposed Design Flow ․ Floorplan and P/G Network Co-Synthesis Algorithm ․ Experimental Results 3

I ntroduction ․ As technology advances, the metal width decreases while the global wirelength increases. Also, supply voltage is decreasing and the power density keeps increasing. ․ The trends cause serious P/G network problems: ⎯ Voltage (IR) drop violation: serious IR-drop on a P/G network � Slow down clock rate and cause functional error Power Integrity Constraints ⎯ Electron-Migration (EM) violation: severe current density through a P/G wire IR-drop constraint: < 0.18V module EM constraint: < 5mA/ µm � Shorten chip lifetime 1.79V 1.59V Power pad 1.8 mA/µ Power EM violation m strap 2.5 mA/µ I R-drop violations m 5.8 mA/µm 1.8V Power 1.8 mA/µm trunk 1.76V 1.6V 1.73V Power pin 4

Previous Work ․ Power integrity issues are dealt at post-layout Traditional DAC 1998 DAC 1999 DAC 2004 stage in the traditional design flow ⎯ P/G network topology determination Prefloorplan Floorplanning Floorplanning Floorplanning Planning Singh, et al., ISPD-04 � Floorplanning Place and Route P/G Planning P/G Analysis ⎯ P/G wire sizing P/G routing � Wang and Shadoska, DAC-03, N Post-Floorplan P/G Analysis OK? � Chowdhury et al., DAC-89 Analysis & Fix Post-Layout ․ As the design complexity increases, it is Y N Optimization OK? Place and Route necessary to handle P/G network problems earlier Place and Route P/G Optimization Y ⎯ Dharchoudhury et al., DAC-98 Post-Layout Place and Route � Pre-floorplan, post-floorplan and post-layout Post-Layout Post-Layout Verification P/G networks analysis and fix Verification Verification P/G analysis P/G Analysis ⎯ Yim et al., DAC-99 Post-Layout N Verification � Post-floorplan P/G networks planning N OK? OK? ⎯ Wu and Chang, DAC-04 Y Y � Iterative tree-structured P/G networks verification and fix with floorplan optimization 5

Our Contributions ․ Propose an automatic floorplan and P/G network co-synthesis method ․ Develop a sophisticated model for fast P/G analysis ⎯ Make the co-synthesis design flow possible ․ Develop P/G network aware method to reduce the floorplan solution space ⎯ Improve the runtime by an average of 68% ․ Integrate into a commercial design flow to develop a power integrity driven design flow ⎯ 2.56X faster than the generic Astro design flow 6

Outline ․ Introduction ․ Proposed Design Flow ․ Proposed Design Flow ․ Floorplan and P/G Network Co-Synthesis Algorithm ․ Experimental Results 7

Proposed Design Flow ․ Floorplan & P/G network co-synthesis problem formulation ⎯ Given a set of modules, power consumption data, and power integrity constraints ⎯ Generate a floorplan and a power integrity Floorplan & P/G feasible global P/G network Network Co-Synthesis ․ Significantly improve the design convergence Place and Route Power Power Integrity Consumption Constraints PASSED Post-Layout verification Perform place and route: modules Perform co-synthesis: Perform post-layout verification: Route P/G straps Generate floorplan and Detailed P/G analysis P/G network plan 8

I mplementation of the Design Flow Data preparation RTL ․ Power profile ⎯ Power consumption data of the Cell Lib Design Compiler modules generated by PrimePower Netlist PrimePower ․ Hierarchical circuit partition Hierarchical Power Profile ⎯ Organize the design into hard Partition modules and soft modules Calculate Current according to the hierarchy Consumption Our Floorplanner Post-layout verification Current Model ․ AstroRail Astro P&R & Constraints ⎯ Static cell-level P/G analysis AstroRail 9

Flow Comparison ․ Previous work: Only move the iterative fix to an earlier stage ․ Our work: Further combine P/G planning into floorplanning ⎯ Thousands of floorplans are evaluated in a second ⎯ A very efficient, yet sufficiently accurate P/G network analysis method is needed DAC-99 DAC-04 Ours Floorplanning Floorplanning P/G Planning P/G Analysis Floorplan & P/G Network Co-Synthesis N P/G Analysis OK? N Y OK? Place and Route Place and Route Y Place and Route Post-Layout Post-Layout verification Verification Post-Layout Verification 10

Outline ․ Introduction ․ Proposed Design Flow ․ Floorplan ․ Floorplan and P/G Network and P/G Network Co- -Synthesis Algorithm Synthesis Algorithm Co ․ Experimental Results 11

Overview of the Co-Synthesis Algorithm ․ B*-tree Floorplan Representation and Simulated Annealing (SA) Algorithm ․ P/G network analysis ⎯ Global P/G Network Construction ⎯ P/G Network Modeling ⎯ P/G Network Evaluation ․ Solution Space Reduction Technique (SSR) 12

B*-tree: Compacted Floorplan Representation ․ Chang et al., “B*-tree: A new representation for non-slicing floorplans,” DAC-2k. ⎯ Given a B*-tree, a legal floorplan can be obtained in amortized linear time ⎯ Root: The most left-bottom module ⎯ Left child: the lowest, adjacent block on the right ( x j = x i + w i ) ⎯ Right child: the first block above, with the same x-coordinate ( x j = x i ) n 0 n 0 b 6 b 6 b 5 b 5 n 7 n 7 n 1 n 1 b 9 b 9 b 3 b 3 b 1 b 2 b 1 b 2 b 4 b 4 n 8 n 8 n 2 n 2 n 5 n 5 x 1 = x 0 x 1 = x 0 n 9 n 9 n 3 n 3 n 6 n 6 b 8 b 8 b 0 b 0 b 7 b 7 n 4 n 4 (x 0 , y 0 ) (x 0 , y 0 ) w 0 w 0 x 7 = x 0 + w 0 x 7 = x 0 + w 0 The corresponding B* -tree A compacted floorplan 13

Cost Function for Simulated Anealing ․ Cost function: Wirelength Area P/G cost P/G Density A Ψ = α ⋅ + β ⋅ + γ ⋅ Φ + ω ⋅ W A , 2 D ․ W: wirelength pitch ․ A : area ․ Φ : P/G network cost ․ D pitch : pitch of P/G network Φ / Φ ˆ ⎯ Update by multiplying avg Φ : Average P/G network cost at a temperature ⎯ avg < Φ < Φ ˆ ˆ : , a budget factor for adjusting the density of P/G 0 1 ⎯ networks Φ ˆ Small for low P/G density and large one for high P/G density 14

Pitch Updating: An Example ˆ = ․ At the beginning of SA, D pitch = 2 and Φ 0 . 02 ) ⇐ Φ Φ × ․ During SA process, D / D pitch avg pitch 1000 4 100 3 10 2 Φ / Φ ˆ D pitch D pitch avg Φ / Φ ˆ 1 1 avg 0.1 0 SA process 0.01 -1 1 0.1 0.01 0.001 0.0001 0.00001 Temperature Φ / Φ ˆ converges to 1 while temperature cools down avg 15

P/ G Network Cost Φ : P/G network cost IR-drop cost EM cost ∑ v B ∀ ∈ p < θ < Φ = θ ⋅ + − θ ⋅ p P em vi 0 1 ( 1 ) , vi v ∑ B V ∀ ∈ lim, pi P P v ․ B em : set of branches violating electromigration constraints ․ B : total branches of the P/G mesh ․ v pvi : amount of the violation at the pin p vi ․ P : set of all P/G pins ․ P v : set of violating P/G pins ․ V lim,pi : IR-drop constraint of the P/G pin p i 16

P/ G Network Construction ․ For each floorplan, we construct a uniform global P/G network according to D pitch ․ The number of trunks is defined by round[width/D pitch ]+1 and round[height/D pitch ]+1 2X4 uniform P/G network is constructed Floorplan 1+ 1 = 2 Height 1 3+ 1 = 4 1 3 2 Width Calculate the P/G network dimention 17

P/ G Network Modeling Apply static analysis for fast P/G network evaluation ․ Use resistive P/G model ․ Model a P/G pin as a current source ⎯ Current value: maximum current drawn from a P/G pin ․ Reduce circuit size ⎯ Connect each current source to the nearest global trunk node Reduced circuit Power pad module Global trunk node Power trunk Power Power pin strap 18

Macro Current Modeling ․ Divide the floorplan into regions ․ For Hard macros ⎯ Connect each P/G pins to the nearest node (center of the region) ․ For Soft macros ⎯ Collect the largest current drawn by standard cells in the overlapping area of the region and the soft macro Assign current to the center Hard module node of the region The border line of the region is defined by the center of the nodes Soft module Overlapping Area d/ 2 d/ 2 d 19

Soft Macro Modeling ․ Derive the largest current drawn by standard cells of the overlapping area ⎯ Maximize the current of the overlapping area ⎯ Constraint: total stdcell area < the overlapping area ⎯ The problem is known as 0-1 Knapsack Problem (NP-complete) ․ Approximate it by Fractional Knapsack Algorithm ⎯ Assume standard cells can be broken into arbitrary smaller pieces ⎯ Rank cells by current to area ratio ⎯ Apply a greedy algorithm (complexity O(n lg n)) Standard cells of the soft module 1mA 1mA 3mA 1mA 1mA 5mA Overlapping Area 4mA 20