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Flexible Displays With Nanostructured Integrated Power Sources M.Peckerar (2) , and Aris Christou (1,3) , (1) Department of Materials Science and Engineering, University of Maryland, College Park, Maryland 20742, USA (2) Dept. Electrical


  1. Flexible Displays With Nanostructured Integrated Power Sources M.Peckerar (2) , and Aris Christou (1,3) , (1) Department of Materials Science and Engineering, University of Maryland, College Park, Maryland 20742, USA (2) Dept. Electrical Engineering, University of Maryland, College Park, Maryland 20742, USA (3) Dept. of Mechanical Engineering, College Park, Maryland 20742, USA

  2. Most Promising Fabrication Methods ► Transfer Printing ► Photolithography with LT Processing

  3. Successful Implementation of Transfer Printing

  4. Second Fabrication Technology For Flexible Electronics ► Photolithography: Flexible polymer attached to a silicon carrier substrate (CS). ► Apply traditional processes but at low temperatures. ► Our work is in the area of flexible displays.

  5. Flexible Displays Outline ► Flexible displays ► Previous work: Flexible Substrates and Identification of Problems ► Experimental Results: Performance and Reliability ► Conclusions Failure: Lineouts due to cyclical deformation

  6. Display Operation Pixel: TFT and Electro-Optical Material Incoming ASIC Video V gate V common C storage V source TF T Bottom
 E lectrode VP OS E lectrophoretic
 Top
 material Gnd Transparent
 electrode Direction
of
 view

  7. Key technological Challenges

  8. Experimental Approach inorder to resolve the issues ► Process Science and Cell Development with Test Wafer Layout Wafer. ► Mechanics of films on flexible substrates ► Specifics of a-Si TFTs ► Metal conductors on a-Si TFTs and power supply for the array. ► Interlayer effects ► Reduction of stress Power Source area ► Modeling stress effects

  9. Low Temp a-Si Process Challenges, Substrate Challenges Background and Motivation ► Impact of Fabrication process on Performance and Reliability. ► 3D Integration of a thin film power cell for tft self bias. ► Stress build up in hydrogenated amorphous silicon thin film transistors on a flexible substrate ► Impact of stresses film delamination cracking / spalling permanent curvature/ warpage of the substrate

  10. On-Substrate Power Source Technology ► Cathode: Mixture of hydrated ruthenium oxide and activated carbon nanoparticles ► Anode: Oxidizing metal (zinc, aluminum…) Flex Substrate ► Capped Electrolyte: Polymeric Membrane Weakly acidic and high viscosity polymer. Electrolyte stabilizing layer And nanoparticle substrate ► Provisional patents: “ Technique for Improving the  ‘ Super-Capacitance ’ of Ruthenium Oxide Based Capacitors ” “ A Flexible, High Specific  Energy Density, Rechargeable Battery ”

  11. The Basic Redox Reaction Ruthenium reduced at the cathode RuO 2 + 2H + +2e - Ru(OH) 2 Via a surface reaction: Zinc oxidized at the anode: Zn Zn ++ + 2e - The cathode reaction is purely a surface reaction: No dissolution of ruthenium occurs RuO 2 -nH 2 0 Nanoparticles, which decorate activated carbon with a binder (about 500nm diameter) The hydrate, RuO 2 -n H 2 O, is a mixed proton– electron conductor, which can generate an ultrahigh pseudocapacitance.

  12. Cross Section of the single sheet Zn-RuO 2 -nH 2 O galvanic cell: 1-Zn electrode, 2: RuO 2 -nH 2 O/activated carbon cathode, 2a-Adhesion layer containing RuOxide nanoparticles, 2b-Graphite film, current collector, 3- separator, 4-packaging substrate

  13. TFT Device Performance

  14. Electrical Measurements: As Processed ► Drive current across entire array ► White dots represent shorted pixels Flex Power Source Flex Power Source Area

  15. Stress Effects / Distortion: Measured During processing and after thermal degradation, As Processed, 100, 1000 Cycles, 1 hr Period (PEN Substrate)

  16. Effect of Strain on Mobility of a-Si TFTs ► Mobility vs strain, Δ T=85C, 100hrs, total, 100 cycles. ► Mobility vs gate orientation ► Performance restored once strain is removed. Mechanics of films on flexible substrates: Temperature Cycling Δ T=85C, 1 hour Periods ► crack networks formed in SiOx coatings on polymer substrates ► PECVD SiOx coatings on PEN substrates ► Failure mode:cracking/ channeling and debonding.

  17. Summary of Effects of strain on TFTs ► Response: elastic deformation -> dielectric fracture ► Electrical function restored once strain is removed ► Compressive strain – mobility reduced ► Tensile strain – mobility increased

  18. Modeling the Mechanical Response ► Internally induced forces  Stress from fabrication, Thermal stress, Humidity stress ► Behavior of film/substrate  Elastic modulus  Thickness of film (d f ), Thickness of substrate (d s ) Strain: built-in and total Built in Strain ε M = ε 0 + ε th + ε ch • ε 0 built in during film growth ε M (total mismatch in strain) ε 0 (built in mismatch in strain) • Atoms deposited in non-euqilibrium ε th = ( α f + α s ) x Δ T positions ( α f + α s ) CTE of film and • When deposited on compliant substrate substrate – can produce strong Δ T (Tdeposition – Troom) curvature ε ch = -( β f - β s ) x %RH • Function of RF power during β = coefficient of humidity deposition (PECVD) expansion

  19. Determining built in strain & stress Film/substrate under compression Extracted from radius of curvature Measure R Determine ε M from previous equation ε M = ε 0 + ε th + ε ch Subtract ε th and ε ch Left with ε 0 Then calculate built in film stress Film/substrate under tension σ f0 = [Y f *Ys*d s / (Y f *d f + Y s *d s )] x ε 0 ► Pre-existing cracks cause crack propagation ► Condition for crack formation under tension ► Films crack more easily when thickness increased ► Γ specific surface energy ► χ depends on elastic constants of film and substrate

  20. Effect of substrates ► Film will conform to the substrate ► Biaxial stress arises in plane of film ► Correlation to mismatch strain  σ f = ε M Y f * , Y f * ε M is the biaxial elastic modulus of film ► Substrate bend with a radius s / 6 σ f d f , Stress is determined by measuring radius R  R = Y s *d 2 Compliant substrates • Substrate also deforms – stress in film reduced If held rigid during fabrication, stress defined as: σ f = ε M Y f */ (1 + Y f *d f /Y s *d s ) σ s = - σ f d f /d s • When carrier is removed, has radius of curvature: R = [(Y s d 2 s - Y f d 2 f ) 2 + 4Y f Y s d f d s (d f + d s ) 2 ] / [6 ε M Y f Y s d f d s (d f + d s )] Y = plane strain elastic modulus

  21. Summary ► General approach: Physics of Failure Approach:Mechanical Strain Limits Determined. ► Results of Present Investigation  PEN and to be extended to stainless steel  Internal stress from fabrication  External stress from life testing ► Power applied ► Elevated temperature ► Potential problems: Mainly Mechanical Reliability? Cyclical Stressing of the substrate results in the main cause of failure. ► Design and integrate a test system to capture time to failure data of thin film interconnects deposited on flexible substrates ► Develop a model to predict cycles to failure based on flexing a substrate to a set radius of curvature. 28

  22. Wafer Test Structures For Fatigue Investigations Common Bus Bar Other test structures ITO Interconnect Pads to Traces interface with driver circuit Thickness ( µ m) Layer Process Process Temp (°C) DC Magnetron Sputtering ITO 0.05 98 SiN 0.3 PECVD 180 29 Planarization 2 Spin coat 230 PEN substrate 125 N/A N/A

  23. Stress-Number of Cycles to Failure Model parameters estimated from TTF data using Maximum Likelihood Estimation (MLE) Life vs Stress 300.000 C y c le s to F a ilu r e 50.000 1.000 10.000 30 Stress (GPa)

  24. Conclusions ► Cyclical Mechanical stress imposed on gate line interconnects root cause of reliability limitations of flexible displays ► Test system designed to capture TTF of interconnects traces subjected to stress ► Life-stress model has been developed to predict reliability of display bent to a set radius of curvature. Fatigue curves developed. Acknowledgements: Industrial Funding (L-3 Communications and The Display Consortium) 31

  25. Future Work ► Different materials  Carbon nanotubes  Organic materials ► Device geometry (interconnect traces)  Accordion  Serpentine ► Fabrication process conditions (lower temp) ► Different processes techniques: Transfer Printing.

  26. Acknowledgements ► Thomas Martin: Phd Student ► The ASU display group and the Federal Display Center for wafer processing. ► Army Research Lab, and the NSF. ► Professors Tang Li, Neil Goldstein of UMD, for their interest in the problem. ► M. Hines for his work in the area of Transfer Printing technology.

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