FE65-P2 Timing Dispersion Student Instrumentation Meeting Katie - PowerPoint PPT Presentation

FE65-P2 Timing Dispersion Student Instrumentation Meeting Katie Dunne Dec 2 , 2016

FE65-P2: Overview 8 chips in 1 2x2 Analog Pixels Prototype Pixel Readout Digital Region Chip: Successor to FE-I4 Predecessor to RD53A 2

Hybrid Pixel Detectors Sensor bump bonded to Charge is collected pads surrounding analog front ends 3

FE65-P2: Overview Tests done on chip without sensor: hit is simulated with injected charge Clock Sensor Comparator Pre-Amp Q Thr | ToT | Digital Region V Thr 4

Propagation of Delay 5

Delay Injection -> Amplifier Constant Sensor Comparator Pre-Amp Q Thr Digital Region V Thr 6

Delay Amp -> Crossing Injection -> Threshold Amplifier Varies with Constant size of hit Sensor Comparator Pre-Amp Q Thr Digital Region V Thr 7

Delay Amp -> Crossing Crossing Threshold Injection -> Threshold -> Comp output Amplifier Varies with Varies with Constant size of hit Comparator Current Sensor Comparator Pre-Amp Q Thr Digital Region V Thr 8

PlsrDelay Measurements 9

Per Pixel Delay PlsrDelay is a 256 bit register with each bit corresponding to a specific delay in nanoseconds Global Latency chosen so that sweeping through PlsrDelay settings 0->255 gives rising and falling edge in hit occupancy for each pixel PlsrDelay scan is run at different Comparator currents -> controlled by voltage bias: CompVbn Mean delay in ns of each pixel is recorded 10

PlsDelay Measurements Measuring 1 bunch crossing Width of each box = 25ns Dispersion is std deviation of mean of all pixels in a Column Flavor 11

Setting -> Delay Conversion Delay settings 0->255 must be converted to ns Injection Clock PlsrDelay step size in Measure Δt between clock & injection nanoseconds is a property of test at each PlsrDelay setting board 12

Setting -> Delay Conversion Delay [ns] Setting Calibration: 0.359x + 17.6 PlsrDelay Setting 13

CompVbn: 60 Mean Delay [ns] Row Column 14

CompVbn: 50 Mean Delay [ns] Row Column 15

CompVbn: 40 Mean Delay [ns] Row Column 16

CompVbn: 25 Mean Delay [ns] Row Column 17

CompVbn: 10 Mean Delay [ns] Row Column 18

Column Flavor Dispersion 19

Next Steps Compare how mean changes with Comparator current -> have to make latencies comparable PlsrDelay scans with different Pre-Amp current setting 20

FE65-P2 Clock Sensor Comparator Pre- Pre-Amp Comparator Q Thr TDAC P Q Thr TDAC N | ToT | Digital Region