Institute for Applied Information Processing and Communications (IAIK) Fast Multi-Precision Multiplication for Public-Key Cryptography on Embedded Microprocessors Michael Hutter and Erich Wenger CHES 2011 Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology TU Graz/Computer Science/IAIK/VLSI/Name TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 Project 1 1
Institute for Applied Information Processing and Communications (IAIK) What is this talk about? � New multiplication technique: � Operand-Caching Multiplication � Idea: trade load against less store instructions by caching of operands � Result: 10% improvement compared to related work on the ATmega128 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 2
Institute for Applied Information Processing and Communications (IAIK) Multi-Precision Multiplication � Most important operation in PKC � Applied in modern processors (8, 16, 32, 64 bits) � Optimizations � Reduce expensive operations � Minimize number of load and/or store instructions TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 3
Institute for Applied Information Processing and Communications (IAIK) Operand Scanning � “Schoolbook method” � a * b = c t � Row-wise processing � 2 loops � Example: n=8 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 4
Institute for Applied Information Processing and Communications (IAIK) Operand Scanning � “Schoolbook method” � a * b = c t � Row-wise processing � 2 loops � Example: n=8 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 5
Institute for Applied Information Processing and Communications (IAIK) Operand Scanning � “Schoolbook method” � a * b = c t � Row-wise processing � 2 loops � Example: n=8 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 6
Institute for Applied Information Processing and Communications (IAIK) Operand Scanning � “Schoolbook method” � a * b = c t � Row-wise processing � 2 loops � Example: n=8 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 7
Institute for Applied Information Processing and Communications (IAIK) Operand Scanning � “Schoolbook method” � a * b = c t � Row-wise processing � 2 loops � Example: n=8 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 8
Institute for Applied Information Processing and Communications (IAIK) Product Scanning TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 9
Institute for Applied Information Processing and Communications (IAIK) Hybrid Multiplication d f=3d+2 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 10
Institute for Applied Information Processing and Communications (IAIK) Operand-Caching Multiplication b init TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 11
Institute for Applied Information Processing and Communications (IAIK) Operand-Caching Multiplication Row 0 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 12
Institute for Applied Information Processing and Communications (IAIK) Operand-Caching Multiplication Row 1 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 13
Institute for Applied Information Processing and Communications (IAIK) Operand-Caching Multiplication e f=2e+3 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 14
Institute for Applied Information Processing and Communications (IAIK) Operand-Caching Multiplication Part 1 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 15
Institute for Applied Information Processing and Communications (IAIK) Operand-Caching Multiplication Part 2 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 16
Institute for Applied Information Processing and Communications (IAIK) Operand-Caching Multiplication Part 3 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 17
Institute for Applied Information Processing and Communications (IAIK) Operand-Caching Multiplication Part 4 TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 18
Institute for Applied Information Processing and Communications (IAIK) Complexity TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 19
Institute for Applied Information Processing and Communications (IAIK) Results � 160-bit multiplication on the ATmega128 � Unrolled instructions TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 20
Institute for Applied Information Processing and Communications (IAIK) Comparison with Related Work � Note: Scott et al. unrolled the instructions TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 21
Institute for Applied Information Processing and Communications (IAIK) Let‘s summarize… …it‘s faster… TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 22
Institute for Applied Information Processing and Communications (IAIK) Let‘s summarize… …it’s more energy efficient… TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 23
Institute for Applied Information Processing and Communications (IAIK) Let‘s summarize… …it outperforms existing solutions! TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 24
Institute for Applied Information Processing and Communications (IAIK) Thank you! Michael Hutter IAIK – Graz University of Technology michael.hutter@iaik.tugraz.at www.iaik.tugraz.at TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 25
Institute for Applied Information Processing and Communications (IAIK) Recent Results � Performance on the 32-bit ARM 7 � 192-bit multiplication � 441 clock cycles needed � 10% improvement compared to related work � Scott et al. reported 487 cycles TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 26
Institute for Applied Information Processing and Communications (IAIK) Memory-Access Complexity TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 27
Institute for Applied Information Processing and Communications (IAIK) Performance for Larger Integers TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 28
Institute for Applied Information Processing and Communications (IAIK) Available Registers TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 29
Institute for Applied Information Processing and Communications (IAIK) 160-bit Multiplication TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011 30
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