Computer Science 12 Design Automation for Embedded Systems Evaluation of resource Evaluation of resource arbitration methods for arbitration methods for multi-core real-time systems multi-core real-time systems Paper presentation at WCET Workshop 2013, Paris Timon Kelter, Tim Harde, Heiko Falk Peter Marwedel Department of Computer Science Institute of Embedded Systems/ Real-Time Systems TU Dortmund, Germany Ulm University, Germany
Computer Science 12 Design Automation for Embedded Systems Predictability for Multicore-Platforms Predictability for Multicore-Platforms Timing influence of parallel task execution Major problem: Contention on shared resources Option 1: Reduce sharing / Duplicate ressources → Wastes economic potential, some communic. is unavoidable Option 2: Provide deterministic and analyzable arbitration → Needs new analysis methods Basic block → Local bounds for runtime arbitration delay of Memory individual accesses access Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 2
Computer Science 12 Design Automation for Embedded Systems Predictability for Multicore-Platforms Predictability for Multicore-Platforms Timing influence of parallel task execution Major problem: Contention on shared resources Option 1: Reduce sharing / Duplicate ressources → Wastes economic potential, some communic. is unavoidable Option 2: Provide deterministic and analyzable arbitration → Needs new analysis methods Basic block → Local bounds for runtime arbitration delay of Memory individual accesses access Arbitration delay Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 3
Computer Science 12 Design Automation for Embedded Systems Outline Outline 1) System model 2) Arbitration methods 3) Analysis framework 4) Benchmark Setup 5) Evaluation 6) Summary Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 4
Computer Science 12 Design Automation for Embedded Systems System model System model Core 1 Core N ARM7TDMI Core ARM7TDMI Core … D-SPM I-Cache D-Cache D-SPM I-Cache D-Cache I-SPM I-SPM Bridge Bridge Shared bus with configurable arbitration Implemented in I-RAM D-RAM BootROM (Uncached) (Uncached) CoMET/Virtualizer [8] L2 I-Cache L2 D-Cache → Flexible experi- I-RAM D-RAM mentation platform (Cached) (Cached) Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 5
Computer Science 12 Design Automation for Embedded Systems Bus arbitration methods Bus arbitration methods „Classic“ methods (Utilization) Fixed Priority (PRIO) p i i Priority value for each core (non-preemtable access) Fair (Round-Robin) (FAIR) → Comparison of achieveable – WCET Time-triggered methods (Predictability) – ACET Time-Division Multiple Access (TDMA) – Bus Utilization n l o j j Slots of length , owner core for each slot o 1 = 1 o 2 = 2 o 3 = 3 o 4 = 4 Priority Division (PD) i j n l p ij Slots of length , priorities for core in slot p 11 = max p 22 = max p 33 = max p 44 = max Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 6
Computer Science 12 Design Automation for Embedded Systems Bus arbitration methods Bus arbitration methods „Classic“ methods (Utilization) Fixed Priority (PRIO) p i i Priority value for each core (non-preemtable access) Fair (Round-Robin) (FAIR) Time-triggered methods (Predictability) Time-Division Multiple Access (TDMA) n l o j j Slots of length , owner core for each slot o 1 = 1 o 2 = 2 o 3 = 3 o 4 = 4 Priority Division (PD) i j n l p ij Slots of length , priorities for core in slot p 11 = max p 22 = max p 33 = max p 44 = max Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 7
Computer Science 12 Design Automation for Embedded Systems Memory hierarchy analysis options Memory hierarchy analysis options Employed approach: Generalized combined analysis ([4], aiT) Core 1 Per-core CFG-based data CFG Reconstruction flow analysis Value Analysis Memory accesses are handled by hierarchical L2 Cache State Merge Combined Microarchitectural Analysis state update Each stage may forward or L1 Cache State Update handle (e.g. guaranteed Pipeline cache hit) State Shared Bus State Update Timing information is Update exchanged along with L2 Cache State Update general access information Path Analysis Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 8
Computer Science 12 Design Automation for Embedded Systems Shared Bus Analysis Shared Bus Analysis What is the “state” for the shared bus? → Approximation of the current position in the cyclic schedule Position: Offset from the beginning of the last TDMA period … Core 1 Slot Core 2 Slot Core 3 Slot Core 4 Slot … x + 1 ⋅ l x + 2 ⋅ l x + 3 ⋅ l x + 4 ⋅ l x Time 1 ⋅ l 2 ⋅ l 3 ⋅ l 0 0 Offsets Abstract Bus State transfer in ⊆{ 0,... ,n ⋅ l − 1 } out Abstraction: Set of offsets O b O b Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 9
Computer Science 12 Design Automation for Embedded Systems Shared Bus Analysis (TDMA & PD) Shared Bus Analysis (TDMA & PD) Transfer function for the shared bus state? a i T a i a i − 1 Pipeline analysis passes in access with spent time since Forwarding to next stages yields post-bus runtime D i + 1 = ∪ O b {Φ c ( o + t mod n ⋅ l )}⊕ D i ,t ∈ T a i o ∈ O b TDMA ( o )= { { o } if o ∈ω must grant immediately Φ c {⌊ω must ⌋} else PD ( o )= { { o }⊕{ 0, … ,m max − 1 } if o ∈ω must Φ c φ c (ω( o )→ω must )∪{⌊ω must ⌋} if ∃ω must ∅ else Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 10
Computer Science 12 Design Automation for Embedded Systems Shared Bus Analysis (TDMA & PD) Shared Bus Analysis (TDMA & PD) Transfer function for the shared bus state? a i T a i a i − 1 Pipeline analysis passes in access with spent time since Forwarding to next stages yields post-bus runtime D i + 1 = ∪ O b {Φ c ( o + t mod n ⋅ l )}⊕ D i ,t ∈ T a i o ∈ O b TDMA ( o )= { { o } if o ∈ω must Φ c {⌊ω must ⌋} else wait for grant window begin PD ( o )= { { o }⊕{ 0, … ,m max − 1 } if o ∈ω must Φ c φ c (ω( o )→ω must )∪{⌊ω must ⌋} if ∃ω must ∅ else Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 11
Computer Science 12 Design Automation for Embedded Systems Shared Bus Analysis (TDMA & PD) Shared Bus Analysis (TDMA & PD) Transfer function for the shared bus state? a i T a i a i − 1 Pipeline analysis passes in access with spent time since Forwarding to next stages yields post-bus runtime D i + 1 = ∪ O b {Φ c ( o + t mod n ⋅ l )}⊕ D i ,t ∈ T a i o ∈ O b TDMA ( o )= { Grant, with possible { o } if o ∈ω must Φ c lower prio access {⌊ω must ⌋} else PD ( o )= { { o }⊕{ 0, … ,m max − 1 } if o ∈ω must Φ c φ c (ω( o )→ω must )∪{⌊ω must ⌋} if ∃ω must ∅ else Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 12
Computer Science 12 Design Automation for Embedded Systems Shared Bus Analysis (TDMA & PD) Shared Bus Analysis (TDMA & PD) Transfer function for the shared bus state? a i T a i a i − 1 Pipeline analysis passes in access with spent time since Forwarding to next stages yields post-bus runtime D i + 1 = ∪ O b {Φ c ( o + t mod n ⋅ l )}⊕ D i ,t ∈ T a i o ∈ O b TDMA ( o )= { Wait for “own” slot, { o } if o ∈ω must Φ c collect “may”-slot offsets {⌊ω must ⌋} else PD ( o )= { { o }⊕{ 0, … ,m max − 1 } if o ∈ω must Φ c φ c (ω( o )→ω must )∪{⌊ω must ⌋} if ∃ω must ∅ else Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 13
Computer Science 12 Design Automation for Embedded Systems Shared Bus Analysis (TDMA & PD) Shared Bus Analysis (TDMA & PD) Transfer function for the shared bus state? a i T a i a i − 1 Pipeline analysis passes in access with spent time since Forwarding to next stages yields post-bus runtime D i + 1 = ∪ O b {Φ c ( o + t mod n ⋅ l )}⊕ D i ,t ∈ T a i o ∈ O b TDMA ( o )= { { o } if o ∈ω must Φ c No “own” slot exists {⌊ω must ⌋} else → Not boundable PD ( o )= { { o }⊕{ 0, … ,m max − 1 } if o ∈ω must Φ c φ c (ω( o )→ω must )∪{⌊ω must ⌋} if ∃ω must ∅ else Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 14
Computer Science 12 Design Automation for Embedded Systems Pessimistic Analyses (PRIO & FAIR) Pessimistic Analyses (PRIO & FAIR) Local bounds for PRIO & FAIR: Need all parallel access interleavings (parallel analysis) → Revert to worst-case assumptions in per-core analysis PRIO ( o )= { { o }⊕{ 0, … ,m max − 1 } if c is max prio core Φ c ∅ else FAIR ( o )={ o }⊕{ 0, … , ( n − 1 ) Φ c ⋅ m max − 1 } Analogous to PD cases Φ c Arbitration delay bound function analogous to → Transfer & Meet (Set union) functions for DFA Kelter, Harde, Marwedel and Falk: “Evaluation of resource arbitration methods […]“ 15
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