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Energy-Efficient In-Memory Data Stores on Hybrid Memory Hierarchies Eleventh International Workshop on Data Management on New Hardware June 2015 Ahmad Hassan (SAP), Hans Vandierendonck (QUB) and Dimitrios S. Nikolopoulos (QUB) May 2015


  1. Energy-Efficient In-Memory Data Stores on Hybrid Memory Hierarchies Eleventh International Workshop on Data Management on New Hardware June 2015 Ahmad Hassan (SAP), Hans Vandierendonck (QUB) and Dimitrios S. Nikolopoulos (QUB) May 2015

  2. Presentation structure  Research Problem  Proposed Solution  Methodology  Evaluation  Conclusion

  3. Research Problem

  4. Processor technology has evolved faster than Main Memory 4. Main Memory DRAM Technology Limitations 3. More Capacity 1. More Processor Demand Cores Technology Evolution 2. More Parallelism Research problem Proposed solution Methodology Evaluation Conclusion

  5. Every 2 years, there is a 30% relative decrease in Main Memory DRAM capacity per processor core ISCA 2009: web.eecs.umich.edu/~twenisch/papers/isca09-disaggregate.pdf Research problem Proposed solution Methodology Evaluation Conclusion

  6. DRAM has technology limitations – physical scalability limits and inefficient power consumption Technology Scaling for Large Memory Capacity: Scalability DRAM has hit scaling limit (Hard to scale below 40 nm) [ITRS. International Technology Roadmap for Semiconductors, 2011] Main memory subsystem energy: Power- DRAM-based main memory consumes 30-40% of the total inefficiency server power [L. A. Barroso et al. Synthesis Lectures on Computer Arch. 2009] Research problem Proposed solution Methodology Evaluation Conclusion

  7. Different Main Memory Technologies Feature DRAM RRAM STTRAM PCM 6 – 8 𝐺 2 > 5 𝐺 2 37 𝐺 2 8 – 16 𝐺 2 Cell Size Read Latency ~30ns ~116ns ~105ns ~151ns Write Latency ~30ns ~145ns ~77ns ~396ns Read Energy* 5.90 4.81 16.60 80.41 Write Energy* 12.70 13.80 21.05 418.6 Static Energy YES Negligible Negligible Negligible Byte-Addressable YES YES YES YES > 10 8 > 10 15 > 10 5 > 10 15 Write Endurance *Read/write Energy is presented in nanojoule per 32 byte access http://www3.pucrs.br/pucrs/files/uni/poa/facin/pos/relatoriostec/tr060.pdf http://dl.acm.org/citation.cfm?id=2742854.2742886 Research problem Proposed solution Methodology Evaluation Conclusion

  8. All this means is that, DRAM is not a viable choice for applications that demand large memory Research problem Proposed solution Methodology Evaluation Conclusion

  9. And our research problem becomes…. DRAM is not a viable choice for applications that demand large memory Can Non-Volatile Memories (NVM) present a better alternative? Research problem Proposed solution Methodology Evaluation Conclusion

  10. Proposed Solution

  11. Before we dive down further, let’s quickly re -cap what an NVM is NVM (Non-volatile memory) is an emerging main memory technology that is byte-addressable like DRAM Research problem Proposed solution Methodology Evaluation Conclusion

  12. Using NVM over DRAM has key advantages – such as power efficiency Lower leakage power than DRAM Advantage Research problem Proposed solution Methodology Evaluation Conclusion

  13. Using NVM over DRAM has key advantages – such as power efficiency and better scalability Lower leakage power than DRAM Advantage Large capacity and better scalability than DRAM Advantage Research problem Proposed solution Methodology Evaluation Conclusion

  14. However it has its downsides too – NVM has higher latency than DRAM Lower leakage power than DRAM Advantage Large capacity and better scalability than DRAM Advantage Higher latency and dynamic energy than DRAM Disadvantage Research problem Proposed solution Methodology Evaluation Conclusion

  15. So we gather a pure NVM-based approach is not viable either Pure NVM-based solution Research problem Proposed solution Methodology Evaluation Conclusion

  16. Because of the higher latency, and Pure NVM-based solution Challenge! How to use NVM as main memory technology without hitting NVM low latency bottleneck and reducing main memory subsystem’s energy ? Research problem Proposed solution Methodology Evaluation Conclusion

  17. So instead a hybrid NVM/DRAM approach could be the answer we are looking for... Pure NVM-based solution Challenge! How to use NVM as main memory technology without hitting NVM low latency bottleneck and reducing main memory subsystem’s energy ? Proposed Solution: Hybrid NVM/DRAM main memory system…and we’ll explain how… Research problem Proposed solution Methodology Evaluation Conclusion

  18. For such hybrid memory schemes, Application-level data management is useful – because it provides a hardware- independent way to manage data  Data management on Hybrid memory at: 1. Application Level 2. Operating System Level 3. Hardware Level One key finding was that, objects presented more accurate granularity of data than pages Research problem Proposed solution Methodology Evaluation Conclusion

  19. Methodology

  20. Application Instrumentation Application Source Profiling Tool Instrumented Executable Run Benchmark / Collect profiling data Apply Analytical Models for object* placement Modified Application Source * Objects are individual program variables and memory allocations. Research problem Proposed solution Methodology Evaluation Conclusion

  21. Profiling Tool Application Source Code LLVM PASS Adds new instructions to profile loads and stores Instrumented Exe Stats File Memory Profiling Library Register Allocations Loads/Stores All Collected Metric Accesses Memory Loads Cache simulator Off-chip Splay tree Memory Stores Accesses Off-chip Memory accesses Memory Allocations Allocation sizes Callpath Lifetime Research problem Proposed solution Methodology Evaluation Conclusion

  22. Performance and Energy Models  Performance Model 𝐵𝑁𝐵𝑈 𝐸𝑆𝐵𝑁 = 𝜈 𝑠 𝑀 𝑠 + 𝜈 𝑥 𝑀 𝑥 + (1 − 𝜈 𝑠 ) 𝑀 𝑀𝑀𝐷 𝜈 𝑠 and 𝜈 𝑥 are number of main memory read and write accesses respectively, 𝑀 𝑠 and 𝑀 𝑥 are DRAM read and write latencies respectively and 𝑀 𝑀𝑀𝐷 is last level cache latency  Energy Model 𝐵𝑁𝐵𝐹 𝐸𝑆𝐵𝑁 = 𝜈 𝑠 𝐹 𝑠 + 𝜈 𝑥 𝐹 𝑥 + 𝑇 𝑄 𝐸𝑆𝐵𝑁 𝑈 𝜈 𝑠 𝑏𝑜𝑒 𝜈 𝑥 are DRAM read and write access respectively. 𝐹 𝑠 and 𝐹 𝑥 are read and write energies respectively. Research problem Proposed solution Methodology Evaluation Conclusion

  23. Object Placement Algorithm ∆𝐵𝑁𝐵𝐹 = 𝐵𝑁𝐵𝐹 𝐸𝑆𝐵𝑁 − 𝐵𝑁𝐵𝐹 𝑂𝑊𝑁 1. ∆𝐵𝑁𝐵𝑈 = 𝐵𝑁𝐵𝑈 𝐸𝑆𝐵𝑁 − 𝐵𝑁𝐵𝑈 𝑂𝑊𝑁 2. Sort total objects on ∆𝐵𝑁𝐵𝑈 3. 𝑂 𝑂 λ ∆𝐵𝑁𝐵𝑈 ≤ 𝐵𝑁𝐵𝑈 𝐸𝑆𝐵𝑁 4. 𝑗=𝑡+1 𝑗=1 Where λ is a user-configurable parameter Research problem Proposed solution Methodology Evaluation Conclusion

  24. Evaluation

  25. Benchmarks and Simulation Benchmarks  MonetDB – In-memory column store  TPCH analytical queries  Memcached – In-memory key-value store  Twitter and Yahoo Cloud Serving Benchmark Simulation  GEM5 Syscall emulation. 512 MB DRAM, 8GB RRAM  Custom application-level memory allocators for DRAM and RRAM Research problem Proposed solution Methodology Evaluation Conclusion

  26. MonetDB Analysis 1. Research problem Proposed solution Methodology Evaluation Conclusion

  27. MonetDB: Performance Degradation vs Energy Savings (%) (%) 94 50 NVM SWP RaPP NVM SWP RaPP 45 92 40 35 90 30 88 25 20 86 15 10 84 5 82 0 Q9 Q18 Q21 Q9 Q18 Q21 Energy Savings Performance Degradation Research problem Proposed solution Methodology Evaluation Conclusion

  28. Conclusion  Use of NVM as main memory is inevitable for meeting main memory capacity demands.  Application-level data management provides a hardware independent way to manage data on hybrid memories.  For the workloads we studied, objects provide better granularity than pages for data management on hybrid memory.  Hybrid DRAM / NVM main memory found promising for in-memory data stores.  Future work on dynamic data placement techniques through operator level rules. Research problem Proposed solution Methodology Evaluation Conclusion

  29. Acknowledgements  Nanostreams Project (http://www.nanostreams.eu)  NovoSoft Project (http://www.qub.ac.uk/research- centres/HPDC/Articles/EUMarieCurieFellowshipNovosoft/)

  30. Thank you! Contact information: Ahmad Hassan ahmad.hassan@sap.com

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