Efficient Design Practices for Thermal Management of TSV based 3D IC System Min Ni, Qing Su, Zongwu Tang, Jamil Kawa Synopsys Inc. ISPD 2010, SF, CA 1
Outline • Introduction: TSV based 3D IC • A Review of 3D IC Thermal Management • 3D IC Thermal Evaluation • Thermal Impact of TSV Arrays in Close Proximity to Hotspots • Thermal Effects of TSV as a Function of TSV Density • Summary & Conclusions 2
TSV based 3D IC – Two Configurations • Vertical Stacking (source: IMEC) – Includes face-to-face, and face-to-back (with TSV) stack. • Lateral Interposer (source: Panasonic) 3
3D (TSV) IC Design Flow • Thermo-mechanical Mfg. TSV Modeling stress analysis • Electrical variation Stress & Reliability Modeling Synthesis & • TSV connectivity checking w/JTAG DFT • 1000x compression TSV 3D IC Design & Verification Bumps Physical • Multi-die bump & TSV floorplan Design • TSV P&R Parasitic • Extract TSV, u-bump, backside Extraction RDL metal Physical Physical Design • TSV aware LVS/DRC Verification 3D Stacked Device • TSV aware timing, Stack IR-Drop, EM Sign-off analysis • Thermal analysis* *application dependent 4
Background EDA Design Methodology • System level • Vertical stacking design Die (Stack) TCAD exploration Partitioning • Logic partitioning exacerbates thermal • TSV problem connectivity Synthesis & checking Thermal impact w/JTAG DFT On mechanical • Test methods – Higher peak characteristics overlappi ng hotspots temperature • Multi-die bump from Physical & different TSV floorplan Design • Auto TSV P&R dies – Risk of hotspot • IC-Package I/F Timing/Power Analysis alignment • Extract TSV, Extraction u-bump, – Performance and backside RDL metal Packaging reliability implications Physical • TSV aware • Thermal management physical Verification verification needed early in design -power integrated -thermal (run • TSV aware system Stack away) timing, flow evaluatio IR-Drop, EM -electrical Sign-off analysis n • Thermal analysis 5
Thermal Management Perspectives • Thermal vias & thermal TSVs – Pros • can utilize existing vias and TSVs • no additional processing steps needed – Cons • non-scalable due to vertical heat path. • area penalty for extra thermal TSVs • Fluidic channels – pros • scalable with chip area and number of tiers – cons • design complexity • Extra reliability • needed vertical resources 6
TSVs • TSVs – Signal TSVs – PG TSVs – Thermal TSVs – Single uniform diameters 7
Thinking Loud • Placement of TSVs – Use TSV array clusters to minimize area penalty on silicon and interconnect – Need to pay attention to mechanical structural balance in TSV placement • Are dedicated thermal TSVs really needed? A single TSV and a TSV – Introduced at design planning stage? array. Exclusion zone is • Academia papers on inserting extra TSVs minimum space of TSV to suggests so active devices- usually 5um – hotspots are not necessarily known at this stage – In post routing stage? • Hotspots are known – Better assessment of need for extra TSVs – Exploit metal density and PGS TSVs requirements – proximity to hotspot planning 8
Thermal Simulation Considerations • Consider whole system vs. 1 die at a time – Eliminates artificial boundary conditions – Eliminates need for large number of iterations • Smaller run time • Used numerically based thermal simulator solving a ciruit-equivalent thermal network – heat source is analogous to a circuit’s current source – thermal resistance is analogous to electric resistance – temperature gradient is analogous to electric potential (voltage) in circuits 9
An EDA Evaluation of a Thermal Structure – Our Experiments Setup die 1 power map 3D-IC system database die 1 thermal resistance network design die 2 power map die 2 thermal resistance . network design . . . . die 3 power map . die N thermal resistance network design package thermal resistance network design 10
Thermal circuit equivalence Max. temperature near Min. temperature near heat source dissipation surface R 12 V 1 V 2 I 12 R 2 R 1 I s -I d =-kV 2 • R 1 is the relative thermal resistivity between the heat source and ambient • R 2 is the relative thermal resistivity between the dissipation surface and ambient. • R 12 is the effective thermal resistivity between the hot spots and cold spots 11
Setup 6x6 mm2 50um thin silicon substrate Added “connectivity” to heat sink makes thermal TSVs, in experiment 12
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; TIER { 3D IC construction TYPE = DIE NAME = die2 COPY = null DB_PATH = /remote/atg5/mni/sandbox2/PR_TA_Lab ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; RDF = ta_cfg.rdf TIER { FLIP = XFLIP TYPE = BUMP XCRD = 0 NAME = die1_die2 YCRD = 0 ;dimension of the bump array POWER_RAMPUP = dieb.prp XDIM = 10 DEBUG_PMAP = dieb.map YDIM = 10 DEBUG_THNET = dieb.mtx DIAMETER = 15 } PITCH = 20 ;thickness of the bump layer THICK = 30 XCRD = 0 YCRD = 0 TCCU = 273 TCOX = 66 DEBUG_THNET = bump_diea_dieb.mtx } ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; TIER { TIER { TYPE = DIE ; TYPE = TSV NAME = die1 NAME = tsvLayer COPY = null NARRAY = 2 ARRAY { DB_PATH = THRGH = NO /remote/atg5/mni/sandbox2/PrimeRail_TA_Lab START = dieA RDF = ta_cfg.rdf XDIM = 5 XCRD = 0 YDIM = 5 YCRD = 0 XCRD = 10 FLIP = NFLIP YCRD = 20 POWER_RAMPUP = diea.prp DIAMETER = 15 DEBUG_PMAP = diea.map PITCH = 20 DEBUG_THNET = diea.mtx TCON = 273 } } } 13
Thermal effects of TSVs in close proximity to hotspots Top view Die 1 Die 2 Before and after TSV array insertion 14
Impact of signal/power TSV array on temperature of 3D IC with different size (one array for each of the 4 hot spots) A single TSV and a TSV array. Exclusion zone is minimum space of TSV to active devices- usually 5um 160 MaxT MinT The maximum temperature decreases as Temperature ( °C) 140 DeltaT TSVs are inserted, however, the effects 120 saturate quickly. The minimum temperature does not drop. 100 80 The net effect of TSV insertion in 3D IC is to reduce the peak temperature and the 60 temperature gradient. 40 0 0.005 0.01 0.015 0.02 0.025 0.03 TSV area as a ratio to die area (%) 15
TSV thermal effects as a function of TSV density with different size (one array for each of the 4 hot spots) 70 68 SP TSVs 65 Delta Temperature ( °C) Thermal TSV 67 60 66 Delta Temperature ( °C) 65 single TSV 55 64 10x10 array 50 63 62 45 61 40 60 0 0.01 0.02 0.03 59 0 200 400 600 800 1000 TSV area as a ratio of die area (%) distance from TSVs to hotspots (um) The ability of reducing thermal gradient is similar for both signal/power TSV and thermal (direct Relation between the distance from connection to sink)TSV arrays. TSVs to hotspots and the reduction of temperature gradient. 16
Summary • Signal and power TSV arrays are practically as efficient as thermal TSVs. • The proximity of thermal TSV arrays to hot spots is more critical than array size. Also, for close proximity arrays size matters but benefits from increased array size saturates quickly. • Better practice is to place TSVs in array format to minimize area penalty, close to hotspot to maximize heat conduction, with compliance to other mechanical and electrical constraints • It is the boundary heat transfer coefficient that dictates the steady state temperature of chips, not the amount of TSVs 17
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