EDA482/487: Machine- Oriented Programming Lecture 7: Timing & - PowerPoint PPT Presentation

EDA482/487: Machine- Oriented Programming Lecture 7: Timing & Synchronization Pedro Moura Trancoso ppedro@chalmers.se Original slides by Ulf Assarsson

Objectives • Topics: • Access Time • Synchronous/Asynchronous Interface • Time diagram • System Clock "SysTick" • Examples • Reading: • “Arbetsbok” chapter 5 • Datasheet "ASCII-display" 4/17/18 Chalmers 2

Previous Lecture • Pointers • Address/Content • Absolute Address - Ports • Pointers as function parameters • Arrays int arrayOfArrays[3][4]; … • Multi-dimentional Arrays arrayOfArrays[i][j] = 10; // OR arrayOfArrays+i*4+j = 10; … 4/17/18 Chalmers 3

Strings (again…) str has memory space allocated automatically and initialized to string ”hello” #include <stdio.h> x points to read-only ”hello” int main() { string. char str[] = "hello"; char *x = "hello"; printf("Before str=%s\n", str); str[1] = 'o'; printf("After str=%s\n", str); Bus Error! printf("Before x=%s\n", x); x[1] = ’o'; printf("After x=%s\n", x); return 0; } 4/17/18 Chalmers 4

Void Pointer (1) #include <stdio.h> int main() { int a=10; float b=35.75; void *ptr; // Declaring a void pointer ptr=&a; // Assigning address of integer to void pointer. printf("The value of integer variable is= %d",*( (int*) ptr) ptr=&b; // Assigning address of float to void pointer. printf("The value of float variable is= %f",*( (float*) ptr) ); } Examples from http://www.circuitstoday.com/void-pointers-in-c 4/17/18 Chalmers 5

Void Pointer (2) void funct(void *a, int z) { if(z==1) printf("%d",*(int*)a); // If user inputs 1, then he means the data is an integer else if(z==2) printf("%c",*(char*)a); // Typecasting for character pointer. else if(z==3) printf("%f",*(float*)a); // Typecasting for float pointer } IMPORTANT: void *ptr; int a; ptr=&a; ptr++; // This statement is invalid and will result in an error because 'ptr' is a void pointer variable. Examples from http://www.circuitstoday.com/void-pointers-in-c 4/17/18 Chalmers 6

Access Time for Different Units DRAM 100 000 CPU 10 000 1 000 ROM 100 EPROM 10 DRAM 1 1980 1990 2000 2010 SRAM Performance gap CPU/DRAM Intel i7-6700: • L1 D$ 32KB + I$ 32KB (4 cycles) • L2 256KB (12 cycles) • L3 8MB (4 core) (42 cycles) • RAM (93 cycles) Highly varying performance results in major differences in access time 4/17/18 Chalmers 7

Unconditional Transfer Requires synchronization - A special signal, "Enable", has to be used to specify exactly when data exchange is to take place. Enable Raising edge Falling edge Raising edge The rising/falling edges define the synchronization. The signal is often called "clock signal" 4/17/18 Chalmers 8

Conditional Transfer The peripheral unit has an interface (register) with a status bit indicating = Asynchronous Transfer whether or not data is available. N Mottagaren Receiver Receiver Mottagaren N Ready? Ready? Redo? Redo? J J Sänd Data Send Data Sänd Data Send Data till mottagaren till mottagaren to receiver to receiver Polling Busy Wait Does not require synchronization but requires special "handshake signals". Therefore, such an interface we call "asynchronous". 4/17/18 Chalmers 9

Synchronous and Asynchronous Interfaces Enable Synchronous : A clock signal from the central unit determines when data exchange occurs Asynchronous : Handshake signals determine when data exchange can occur 4/17/18 Chalmers 10

Time Diagram – Basis for Synchronization Read cycle: data is transferred from peripheral Write cycle: data is transferred from the CPU device to CPU to peripheral device min t c Cycle time min t w Clock pulse ("Enable") duration (high and low) min t su1 control signal setup time, before positive edge min t su2 setup time for data writing, before negative edge min t D Setup time for data, reading, before negative edge max t h Hold time, duration (after negative edge) min 4/17/18 Chalmers 11

Time Diagram – Basis for Synchronization Read cycle: data is transferred from peripheral Write cycle: data is transferred from the CPU device to CPU to peripheral device min Write cycle: Read cycle: 1.Set the R/W-signal to 0 (a bit in a specific port) 1.Set the R/W-bit to 1. t c Cycle time min 2.Wait at least tsu1 ns. 2.Wait at least tsu ns. t w Clock pulse ("Enable") duration (high and low) min 3.Set the enable-bit and wait at least tw ns. 3.Set the enable-bit to 1 4.At least tsu2 ns before reseting the enable-bit, write the data to the 4.Wait at least tD ns. t su1 control signal setup time, before positive edge min data bus (a port) 5.Read from the data bus. t su2 setup time for data writing, before negative edge min 5.Reset the enable-bit. 6.Wait at least tw have passed. 6.Wait at least th ns until starting again (and set R/W). Wait for at 7.Set enable-bit to 0. t D Setup time for data, reading, before negative edge max least a total of tc ns (cycle time). 8.Wait at least th ns. t h Hold time, duration (after negative edge) 9.Modify R/W if you want, but wait for a complete cycle time of tc. min 4/17/18 Chalmers 12

Write Cycle Examples: Interface/Algorithms Data-register Byte to be transfered Read or Write Transfer 8 bits to the ascii controller: synchronization signal Command or ASCII-data Control-register(RW)=0; Wait t su1 ; Control-register(E)=1; Control-register Data-register = (8 bits); Wait t su2 ; (until at least t w passes) E = 0; Wait until a total t c passes; 4/17/18 Chalmers 13

Examples: Interface/Algorithms Write Cycle 1. For example setup port GPIO_E for the ascii-display. 2. The Ascii-display expects: Data-register (bit 8 - 15) => ODR_high-byte Transfer 8 bits to the ascii controller: Control-register (bit 0 - 7) => ODR_low-byte Control-register(RW)=0; Wait t su1 ; Control-register(E)=1; Data-register = (8 bits); Wait t su2 ; (at least until t w passes) Läs eller Synkronisera E = 0; skriv Wait until a total of t c passes; nde signal GPIO_E ODR_High ODR_low 4/17/18 Chalmers 14

Examples: Interface/Algorithms Write Cycle 1. For example setup port GPIO_E for the ascii-display. #define GPIO_E 0x40021000 /* MD407 port E */ 2. The Ascii-display expects: #define portOdrLow ((volatile unsigned char *)(GPIO_E+0x14)) Data-register (bit 8 - 15) => ODR_high-byte #define portOdrHigh ((volatile unsigned char *)(GPIO_E+0x14+1)) Transfer 8 bits to the ascii controller: Control-register (bit 0 - 7) => ODR_low-byte #define B_E 0x40 #define B_SELECT 0x04 #define B_RW 0x02 Control-register(RW)=0; #define B_RS 0x01 Wait t su1 ; Control-register(E)=1; // RS is set to 0 for command or to 1 for data read/write Data-register = (8 bits); *portOdrLow |= B_SELECT; // set the select-bit *portOdrLow &= ~B_RW; // turn off RW Wait t su2 ; (at least until t w passes) Läs eller delay(t_su1= ~40ns); Synkronisera E = 0; *portOdrLow |= B_E; // set enable skriv Wait until a total of t c passes; *portOdrHigh = our 8 bits of data; nde signal delay(max(t_su2=80ns, t_w=240ns); GPIO_E ODR_High ODR_low *portOdrLow &= ~B_E; // reset enable delay( (t_c=500ns) – 240ns); 4/17/18 Chalmers 15

Counting Circuit - "SysTick" Downcounter 24 bits STK_LOAD STK_VAL t Reload Reload Reload 0 4/17/18 Chalmers 16

Counting Circuit - Register Delay(): Algoritm: STK_CTRL = 0 Reset SysTick STK_LOAD = CountValue STK_VAL = 0 Reset the counter register STK_CTRL = 5 Restart the counter Wait until COUNTFLAG=1 STK_CTRL = 0 Reset SysTick 4/17/18 Chalmers 17

Counting Circuit - Register Delay(): 1: Räknare aktiverad Algoritm: STK_CTRL = 0 Reset SysTick STK_LOAD = CountValue Bit0 = 1 (enable) STK_VAL = 0 Reset the counter register Bit1 = 0 (no interrupt) STK_CTRL = 5 Restart the counter Bit2 = 1 (system clock) Wait until COUNTFLAG=1 STK_CTRL = 0 Reset SysTick 4/17/18 Chalmers 18

How many cycles? Example 1: 250 ns delay with “SysTick” 250ns x 168MHz = 42 cycles 1. Create a function delay_250ns(void) which blocks (delays) the calling function by least 250 ns. 2. Also show how this can be used to create a delay routine delay_milli( unsigned int millisec) which delays the application execution by a variable number of milliseconds. void delay_micro(unsigned int us) #define STK_CTRL ((volatile unsigned int *)(0xE000E010)) { #define STK_LOAD ((volatile unsigned int *)(0xE000E014)) while(us--) { #define STK_VAL ((volatile unsigned int *)(0xE000E018)) delay_250ns(); delay_250ns(); void delay_250ns( void ) { delay_250ns(); delay_250ns(); /* SystemCoreClock = 168000000 */ *STK_CTRL = 0; } } *STK_LOAD = ( (168/4) -1 ); *STK_VAL = 0; *STK_CTRL = 5; // delay_milli(): 1 ms = 1000 us void delay_milli( unsigned int ms ) while( (*STK_CTRL & 0x10000 )== 0 ) {} { *STK_CTRL = 0; while( ms-- ) } delay_micro(1000); } 4/17/18 Chalmers 19