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ECS CSEL EL Bro roker erage age Event nt 2016 16 ECSE CSEL - PowerPoint PPT Presentation

ECS CSEL EL Bro roker erage age Event nt 2016 16 ECSE CSEL Joint Undertak aking ng Nano-Imprint Lithography Large Surface Pilot Line RIA Proposal Anneliese Pnninger Courtesy of Fraunhofer ISE a.poenninger@evgroup.com NIL


  1. ECS CSEL EL Bro roker erage age Event nt 2016 16 ECSE CSEL Joint Undertak aking ng Nano-Imprint Lithography “Large Surface” Pilot Line RIA Proposal Anneliese Pönninger Courtesy of Fraunhofer ISE a.poenninger@evgroup.com

  2. NIL – Why and What for? Displays • More than Silicon substrates MEMS (Polymer/Flexible/Sapphire...) OLED LED NEMS • High resolution / Large surface • High throughput • Bio compatible polymers • Polymer for permanent Image Flexible e- applications Sensors • 3D complex shapes • Non flat samples Plasmonic Micro Components Fluidics BioMEMS Solar Cells ECSEL SEL Brok oker erage ge Event nt 2016 2

  3. NIL – Project Concept Market Needs NIL Value Chain End User Request (Master, Equipment, Material, (design / product) Metrology, Integration) Pilot Line Environment Solutions Transferred to (infrastructure building, End Users or Companies solution qualification in the value chain. and integration) ECSEL SEL Brok oker erage ge Event nt 2016 3

  4. A little more technical information about my project  Standardization w.r.t. applications  Fully automated solutions assessed in pilot line environment  what about real alignment capabilities in production regime?  what about the real defectivity levels and what are the real bottlenecks?  Associated metrology (real time is not needed for wafer scale, but in line YES!)  Defectivity assessment w.r.t. applications  “Real” CoO assessment in pilot line in a full process flow (yield, stamp lifetime … ).  Validation of some “elementary modules” that are still missing in the value chain: Stamp Design (w.r.t. process that will be implemented), Stamp Repair, Complete Simulation ToolBox. Demonstrate Industrial Maturity Qualify a well established Supply chain ECSEL SEL Brok oker erage ge Event nt 2016 4

  5. Information about the Consortium • Consortium under construction / RIA call / Total budget 15 M € • NIL technology maturity TRL from 4 (start) to 6 (in 2019) • Materials development, metrology • Device design and manufacturers – Photonics (LED, displays, opto-electronics) – Bio-technology – MEMS, Flexible support, @ wafer level / @ large surface scale level etc. • End-user assessment / Specific Work packages // NIL options. To accelerate adoption of this technology. To demonstrate the benefits of the full-wafer NIL technology and spreading its use for applications beyond the traditional semiconductor industry . ECSEL SEL Brok oker erage ge Event nt 2016 5

  6. Thank you! Anneliese Pönninger A.Poenninger@EVGroup.com, EV Group DI Erich Thallner Str. 1, 4782 St. Florian am Inn, Austria www.EVGroup.com ECSEL SEL Brok oker erage ge Event nt 2016 6

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