E-Beam Lithography Stencil Planning and Optimization With Overlapped - PowerPoint PPT Presentation

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters Kun Yuan, David Z. Pan Dept. of Electrical and Computer Engineering The University of Texas at Austin http://www.cerc.utexas.edu/utda

Outline t Introduction and Motivation › Electronic Beam Lithography (EBL) › Overlapped Characters t EBL Stencil Planning/Optimization › One-Dimensional Stencil Design › Two-Dimensional Stencil Design t Experimental Results t Conclusion 2

Conventional Optical Lithography Light source Illumination Lens masks Projection Lens Wafer

Scaling Woos HP t Aggressive scaling of min. printable half pitch [Smayling+, SPIE 2008] HP λ HP k NA = t λ is stuck at 193nm 1 t k 1 : limit is 0.25 t NA = 1.5, close to the limit k 1 : process difficulty NA: numerical aperture t EUV (13.5nm): Still many, many λ : wavelength of source challenges! 4

Mask Cost !!! Alternative solution for 32nm/22nm and below Mask 1 Mask 2 Double Patterning Or even triple/quadruple patterning! But mask cost will be proportionally higher!

Electron Beam Lithography t Maskless technology, which shoots desired patterns directly into the silicon wafer › 4x better resolution [Solid State Technology 2011] › Lower cost [D2S Inc] Electron Gun The biggest challenge: Shaping aperture Low throughput

Variable Shape Beam (VSB) t One rectangle per shot Electron Gun Electron Gun Shaping aperture Shaping aperture Total number of 11 shots are needed

Character Projection (CP) Technology t Print some complex shapes in one electronic beam shot, rather than writing multiple rectangles. Electron Gun Shaping aperture Stencil Character Wafer

Character Projection Technology (Cont.) Electron Gun Shaping aperture Electron Gun Stencil Shaping aperture Wafer Electron Gun Stencil Wafer Shaping aperture Stencil Only three shots are needed Wafer

Limitation of Character Projection t The number of characters is limited due to the area constraints of the stencil › Various investigations [ Makoto et al. SPIE’06, SPIE’09 ] on optimization of character selection H Character w h W

Overlapped Characters t Blanking space is usually reserved around its enclosed rectangular circuit pattern Spanned region Blank A Blank B of electron beam Layout A Layout B from shaping aperture Character A Character B t By allowing over-lapping adjacent characters, more characters may be put on stencil [Fujimura+, 2010] Min(BlankA, BlankB) BlankA BlankB Layout A Layout B Layout A Layout B Character A Character B Character A Character B

Not a Trivial Task B C A Character Candidates to be Considered Stencil Order Matters Out of A A B B C C Stencil

Problem Definition C t Given a set of character candidates C l j j j i b r j i t i i H V o min( , ) r l o min( , t b ) = = ij i j ij i j r C Each candidate appears in the circuit i i CP VSB n n #shots by VSB: #shots by CP: i i

Problem Definition (Cont.) C t Select a subset out of character CP C candidates , and place them on the stencil S C Minimize total number of shots: CP VSB rn rn ∑ ∑ + i i i i C C C C \ C ∈ ∈ i CP i C CP B C A While C The placement of is CP bounded by the outline of Stencil stencil.

One Dimensional Problem t The required blanking spaces on the top t and bottom b are nearly identical for all the candidates. t t = j i i j 2 r 1 3 b b r r h = j i 1 1 1 h h h − o 1 3 r r 3 r o H 2 2 2 W

Optimization Flow One-Dimensional Bin Packing Single Row Reordering Multi Row Swapping Inter-Stencil Tuning No Yes End Result Improved

One-Dimensional Bin Packing CP VSB rn rn ∑ ∑ + Minimize i i i i C C C C \ C ∈ ∈ i CP i C CP VSB VSB CP rn r n ( n ) ∑ ∑ = − − i i i i i C C C C ∈ ∈ i C i CP Maximize Constant VSB CP r n ( n ) ∑ − i i i Packing by the decreasing order of C C ∈ i CP Put C here? R1 A R1 A R1 A C … . … . … . S1 C < S2 R2 R2 R2 B … . C C B B … . … . W W W Put the candidate into the row with most blacking space left

Single Row Reordering t Adjust the relative locations of already-placed characters in each row to shrink its occupied width and increase remaining capacity Out of A B C Stencil A B C t Transform to min-cost Hamiltonian path problem H H o o − big ji r r r r v v v v A B A B H H o o − big ij A B C r v r v C C

Multi-Row Swapping and Inter-Stencil Tuning t Multi-Row Swapping 2 1 r 3 1 3 r r R1 r 2 r R1 r 1 1 1 1 1 2 2 1 2 r r r 3 r 1 r 3 r Smaller Bigger 2 2 1 R2 2 2 R2 2 t Inter-Stencil Tuning › Exchange the placed characters with those which have not been selected

Two Dimensional Problem t The blanking spaces of templates are non- uniform along both horizontal and vertical directions. t Simulated Annealing Framework with Sequential Pair Representation X Y , are two permutations of characters ( , ... ) c c c 0 1 n X (... ... ...), =(... ... ...). c is left to c c c Y c c = i j i j i j X (... ... ...), =(... ... ...). c is below c c c Y c c = j i i j i j

Transformation from SP to Stencil t Transform SP to a min-area packing solution t Pick the candidates within outline of stencil as characters E(2) E(2) D(2) D(2) C(1) C(1) A(3) A(3) B(2) B(2) X ( ) E D A C B = X ( ) E D A C B = Y ( ) A B D E C = Y ( ) A B D E C =

Throughput-Driven Swapping t Try to reduce the projection time by swapping the positions of two candidates in the X & Y SP. C(1) Stencil E(2) Swap D(2) C and E D(2) C(1) E(2) A(3) A(3) B(2) B(2) X ( ) E D A C B = X ( ) C D A E B = Y ( ) A B D E C = Y ( ) A B D C E =

Slack-Base Insertion t Make use of the concept of slack to find a good position to insert extra candidate into the stencil left right X X C C C C D D A A B B slack right left X X X = − C C C

Slack-Based Insertion t Make use of the concept of slack to find a good position to insert extra candidate into the stencil X ( ) C A D B E X ( ) E C A D B = = Y ( ) A C B D E Y ( ) A E C B D = = C E C D D E A A B B

Experimental Setup t Implemented in C++ t Intel 8 Core Linux, 3.0 Ghz, 32GB t Parquet [TVLSI 2003] is adopted as SA framework t Compare with two baseline methods › ILP-based approach without overlap characters [Sugihar, SPIE 2009] › Greedy bin-packing algorithm with overlap characters 25

Benchmark Circuit Character Size Total area Total blanks Optimal area 4 2 um um 1 e um 4 2 4 2 × 1 e um 1 e um 1D-1 3.8x3.8 1.444 0.416 1.028 1D-2 4.0x4.0 1.6 0.479 1.121 1D-3 4.2x4.2 1.764 0.514 1.25 1D-4 4.4x4.4 1.936 0.569 1.367 2D-1 3.8x3.8 1.444 0.414 1.03 2D-2 4.0x4.0 1.6 0.529 1.071 2D-3 4.2x4.2 1.764 0.662 1.102 2D-4 4.4x4.4 1.936 0.774 1.162 The area of stencil is 100 um 100 um × 1000 character candidates 26

One Dimensional Stencil Design #shots (projection time) #characters on stencil 1000 50000 800 40000 30000 600 20000 400 10000 200 0 0 1D-1 1D-2 1D-3 1D-4 1D-1 1D-2 1D-3 1D-4 NON-OVERLAP GREEDY PROPOSED NON-OVERLAP GREEDY PROPOSED #CPU(logscale) 100 t 51%, 14% reduction on shot 10 number over previous ILP-based 1 approach without overlapping 0.1 characters and greedy algorithm . 1D-1 1D-2 1D-3 1D-4 NON-OVERLAP GREEDY PROPOSED 27

Two Dimensional Stencil Design t 31%, 25% reduction on shot number over previous ILP-based approach without overlapping characters and greedy algorithm . 28

Conclusion t E-Beam Lithography is a promising emerging technology for better resolution and lower cost t Low throughput is its key hurdle t E-beam lithography stencil planning and optimization with overlapped characters t Lots of future research opportunities on physical design and emerging lithography › E-beam multi-stencil optimization problems › Massive parallel e-beams/characters › Double/triple patterning lithography › EUV, …… 29

Acknowledgment t The work is sponsored in Part by NSF, IBM Faculty Award and equipment donations from Intel t Dr. Gi-Joon Nam at IBM Austin Research Lab for helpful discussions. 30