Dynamic Near Data Processing Framework for SSDs Gunjae Koo *, Kiran Kumar Matam*, Te I † , H.V. KrishinaGiri Nara*, Jing Li ‡ , Hung-Wei Tseng † , Steven Swanson ‡ , Murali Annavaram* *University of Southern California † North Carolina State University ‡ University of California, San Diego
Conventional Storage = Cheap Passive Devices Con Conventional s entional stor torage age devices devices Sl Slow ow, , limit limited ed bandwidt bandwidth h (SA (SATA 150 A 150 ~ 600 ~ 600 MB/ MB/s) s) • Pass assiv ive e devices devices (r (read, ead, write, write, er erase ase) • 2 * Figures from Intel and Western Digital
Storage in Modern Server Systems Stor Storage age devices devices for for Big D Big Data ata Huge Huge volumes olumes of of dat data a sl slow ow, , sl slower ower, , much much sl slower ower • Data Data mov movement ement is is critica critical l for for performance performance • 3
Intelligent Storage NVM NVM-based st based stor orage age devices devices No No se seek ek t time, ime, higher higher bandwidt bandwidth h ov over er PCIe PCIe • Potent otential ial to to be a be activ ctive e syst systems ems • 4 * Figures from Intel
Intelligent Storage SSD Processor NAND flash packages NVM-based st NVM based stor orage age devices devices DRAM No No se seek ek t time, ime, higher higher bandwidt bandwidth h (PCIe PCIe) • Potent otential ial to to be a be activ ctive e syst systems ems • 5 * Figures from Intel
Near Data Processing (NDP) Host Stor Storag age Process Proce ssor or CPU CPU Storage interface (SP) (SP) Externa nal (host t – storage age) Inter erna nal Data a computa utation on @ h host Data a transf sfer er fro rom storage age 6
Near Data Processing (NDP) Host Stor Storag age Pr Process ocessor or CPU CPU Storage interface (SP) (SP) Externa nal (host t – storage age) Inter erna nal W/O O NDP NDP Data a computa utation on @ h host Data a transf sfer er fro rom storage age Wi With th NDP NDP Data a computa utation on @ st storage age 7
Near Data Processing (NDP) on SSDs Host SP SP CPU CPU Storage interface Garbage Wear- collection leveling Externa nal (host t – storage age) Inter erna nal W/O O NDP NDP Data a computa utation on @ h host Data a transf sfer er fro rom storage age Wi With th NDP NDP Data a computa utation Data on @ st a computa storage utation age on @ st storage age 8
Near Data Processing (NDP) on SSDs Host Obstacles Obstacles to to in in-SSD pr SSD proces ocessing sing SP SP CPU CPU Storage interface Less Less powerful powerful embedded embedded pr process ocessor or • Garbage Wear- Dynamic computat Dynamic computation ion resour esource ce av availa ailabilit bility • collection leveling Manual work Manual workloa load d pa parti rtitio tioning ning is is difficult difficult • Externa nal (host t – storage age) Inter erna nal Summarize Summarizer: D r: Dynamic ynamic NDP fr NDP framew amework ork for SSD for SSD W/O O NDP NDP Data a computa utation on @ h host Data a transf sfer er fro rom storage age Wi With th NDP NDP Data a computa utation on @ st storage age 9
Summarizer – Basic Concept Host Mo Monito tori ring g reso esour urce ces AP AP CPU CPU Storage interface 10
Summarizer – Basic Concept Host Mo Monito tori ring g reso esour urce ces AP AP CPU CPU Storage interface 11
Summarizer – Detailed Firmware Architecture Host CPU SSD Firmware Summarizer I/O C I/ O Controll ontroller er (NVMe NVMe command command dec decoder oder) User Ap User Appli plications cations / Operating Ope ating Systems Systems Storage Interface (PCIe / NVMe) Flash lash Transla anslation La tion Layer er (F (FTL) TL) Task Control ask Controlle ler SSD Embedded Processors se queue Request queue NVMe NVMe Host Host Driv Driver er Response TQ TQ Host Memory SSD SoC Interconnection Us User r Func unctio tions ns Flash Controller DRAM Controller SQ SQ CQ CQ NAND Flash NAND Flash NAND Flash SSD DRAM NAND Flash 12
Summarizer – Initialization (Function Offloading) Host CPU SSD Firmware Summarizer I/ I/O C O Controll ontroller er (NVMe NVMe command command dec decoder oder) User User Ap Appli plications cations / Ope Operating ating Systems Systems Storage Interface (PCIe / NVMe) Flash lash Transla anslation La tion Layer er (F (FTL) TL) Task Control ask Controlle ler New NVM New NVMe co comman and se queue Request queue NVMe NVMe Host Host Driv Driver er INIT ( foo) Response TQ TQ Fun unct ction r on reg egistr strati ation on Host Memory SSD SoC Interconnection foo() Us User r Func unctio tions ns f#1 foo() Function offlo ction offloadin ding Flash Controller DRAM Controller SQ SQ CQ CQ NAND Flash NAND Flash NAND Flash SSD DRAM NAND Flash 13
Summarizer – Computation (Dynamic mode) New NVMe New NVMe co comman and d de deco code de Host CPU SSD Firmware Summarizer I/O C I/ O Controll ontroller er (NVMe NVMe command command dec decoder oder) User User Ap Appli plications cations / Ope Operating ating Systems Systems Storage Interface (PCIe / NVMe) Flash lash Transla anslation La tion Layer er (F (FTL) TL) Task Control ask Controlle ler RD&PROC(PPA,foo) New NVM New NVMe co comman and se queue Request queue NVMe Host NVMe Host Driv Driver er Response RD&PROC( LBA,foo) TQ TQ Host Memory SSD SoC Interconnection Us User r Func unctio tions ns f#1 foo() Flash Controller DRAM Controller f#2 goo() SQ SQ CQ CQ NAND Flash NAND Flash NAND Flash SSD DRAM NAND Flash 14
Summarizer – Computation (Dynamic mode) Host CPU SSD Firmware Summarizer I/O C I/ O Controll ontroller er (NVMe NVMe command command dec decoder oder) User User Ap Appli plications cations / Operating Ope ating Systems Systems Storage Interface (PCIe / NVMe) Flash lash Transla anslation La tion Layer er (F (FTL) TL) Task Control ask Controlle ler RD&PROC(PPA,foo) se queue Request queue NVMe NVMe Host Host Driv Driver er Response TQ TQ RD&P(PPA2,foo) RD&P(PPA1,foo) RD&P(PPA1,foo) Host Memory SSD SoC Interconnection User Us r Func unctio tions ns f#1 foo() Flash Controller DRAM Controller f#2 goo() SQ SQ CQ CQ NAND Flash NAND Flash NAND Flash SSD DRAM NAND Flash Page data 15
Summarizer – Computation (Dynamic mode) Host CPU SSD Firmware Summarizer I/O C I/ O Controll ontroller er (NVMe NVMe command command dec decoder oder) User User Ap Appli plications cations / Ope Operating ating Systems Systems CC/Proc Storage Interface (PCIe / NVMe) Flash lash Transla anslation La tion Layer er (F (FTL) TL) Task Control ask Controlle ler RD&PROC(PPA,foo) Registe Re ster r in n TQ se queue Request queue NVMe NVMe Host Host Driv Driver er buf1, foo Response TQ TQ RD&P(PPA1,foo) Host Memory SSD SoC Interconnection Us User r Func unctio tions ns f#1 foo1() Flash Controller DRAM Controller f#2 goo() SQ SQ CQ CQ NAND Flash NAND Flash NAND Flash SSD DRAM Page data NAND Flash 16
Summarizer – Computation (Dynamic mode) Host CPU SSD Firmware Summarizer I/O C I/ O Controll ontroller er (NVMe NVMe command command dec decoder oder) User Ap User Appli plications cations / Operating Ope ating Systems Systems CC Storage Interface (PCIe / NVMe) Flash lash Transla anslation La tion Layer er (F (FTL) TL) Task Control ask Controlle ler RD&PROC(PPA,foo) TQ Q is s full full se queue Request queue NVMe NVMe Host Host Driv Driver er Response TQ TQ RD&P(PPA1,foo) Host Memory SSD SoC Interconnection User Us r Func unctio tions ns f#1 foo() Flash Controller DRAM Controller f#2 goo() SQ SQ CQ CQ NAND Flash NAND Flash NAND Flash SSD DRAM Page data NAND Flash 17
Summarizer – Finalization Host CPU SSD Firmware Summarizer I/O C I/ O Controll ontroller er (NVMe NVMe command command dec decoder oder) User User Ap Appli plications cations / Operating Ope ating Systems Systems Storage Interface (PCIe / NVMe) Flash lash Transla anslation La tion Layer er (F (FTL) TL) Task Control ask Controlle ler New New NVM NVMe co comman and se queue Request queue NVMe NVMe Host Host Driv Driver er FINAL ( foo) Response TQ TQ Host Memory SSD SoC Interconnection User Us r Func unctio tions ns f#1 foo() Flash Controller DRAM Controller f#2 goo() SQ SQ CQ CQ NAND Flash NAND Flash NAND Flash SSD DRAM Results NAND Flash 18
Evaluation Platform • LS2085a intelligent SSD development platform • ARM cores running FTL and Summarizer firmware • FPGA implementing NAND flash controller • PCIeGen. 3 4x lanes for host communication LS2085a CPU CPU CPU CPU PCIe (LS2085a - FPGA) PCIe (host – LS2085a) L1D L1I L1D L1I L1D L1I L1D L1I (32KB) (48KB) (32KB) (48KB) (32KB) (48KB) (32KB) (48KB) L2 L2 (1MB) (1MB) FPGA (ALTERA Stratix V) Interconnection DDR4 Memory Controller NAND flash NAND flash DIMM DRAM DRAM DIMMs 19
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