A Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology , Japan IEICE General Conference 2014 2014/3/18
Outline 1 Motivation Conventional ILFDs Proposed Dual-Step-Mixing ILFD using a Direct Injection Technique Performance Comparison Frequency Drift over PVT variations Integration with 20GHz PLL Conclusion 2014/3/18 T. Siriburanon, Tokyo Tech
Background 2 • 9-GHz unlicensed bandwidth at 60 GHz • Several Gbps wireless communication Wireless HD ECMA-387 ISO/IEC13156 IEEE 802.11ad/WiGig IEEE 802.15.3c [1] http://www.tele.soumu.go.jp 2014/3/18 T. Siriburanon, Tokyo Tech
Direct 60GHz Frequency Synthesizer 3 60GHz VCO Ref. Phase/ Charge Low Pass Clock Frequency Pump Filter Detector Digital ÷ N ÷ M Divider High speed frequency dividers Direct 60GHz VCO suffers from inferior phase noise due to Q of tank at 60GHz Power-hungry frequency divider is required 2014/3/18 T. Siriburanon, Tokyo Tech
60GHz Frequency Synthesizers 4 Sub-harmonic injection • 20GHz VCO 60GHz ILO 2 divide-by-2 CML REF PFD CP LPF divider consumes single-stage ÷ 4 15mW (40% of PLL) divide-by-4 ILFD Digital ÷ 2 ÷ 2 Divider [1] A. Musa, et al. , JSSC 2011 60GHz push-push VCO 30GHz VCO Divide-by-3 ILFD + 60GHz REF PFD CP LPF divider chain consumes single-stage more than 50% of PLL ÷ 6 divide-by-6 ILFD Digital ÷ 2 ÷ 3 [2] T. Tsukizawa, et al., ISSCC 2013 Divider 2014/3/18 T. Siriburanon, Tokyo Tech
High-speed Ring ILFD chains 5 Large power 30GHz 5GHz 30GHz 15GHz 5GHz Locking range 2 3 Digital ILFD ILFD Dividers mismatch 30GHz 5GHz Narrow locking 6 Digital ILFD Dividers range 20-GHz PLL needs a divide-by-4 ILFD 30-GHz PLL needs a divide-by-6 ILFD A technique to increase locking range of high-order- division in ILFDs is necessary 2014/3/18 T. Siriburanon, Tokyo Tech
Conventional Direct Mixing Ring ILFD 6 f out LPF f inj = Nf out Nonlinearity ∙∙∙ f out 2 f out ∙∙∙ (N-1)f out f Divide by N directly in one step Injection signal is directly divide by N Low power consumption Narrow Locking range 2014/3/18 T. Siriburanon, Tokyo Tech
Progressive Mixing Ring ILFD (I) 7 f out 2 f out LPF f inj =4 f out Nonlinearity X2 Multi-step mixing mechanism divide-by-2 n operation, e.g. , 2, and 4 Locking range is enhanced through the use of stronger harmonics [3] A. Musa, et al. , A-SSCC 2011
Progressive Mixing Ring ILFD (II) 8 High division ratio ILFD by reusing higher harmonic in cascoded configuration Osc. @ f o 5GHz M5 M6 M7 M8 M1 M2 M3 M4 Osc. @ 2f o M T1 M T2 M T3 M T4 10GHz V bias V bias V bias V bias Tail INJ- Inj. @ 4f o M T5 M T6 INJ+ 20GHz Injection V bias V bias [3] A. Musa, et al. , A-SSCC 2011
Issues of Conventional PMILFD (I) 9 Large headroom ― Impractical for low (For divide-by-8) voltage design 4 x NMOS ― For 1.2 V supply, higher than 8 division is hard to 4 overdrive voltage be achieved required RF8 injection 12 Free Run Frequency Sensitive to PVT due 3GHz 10 to PMOS tuning Difference (GHz) 8 ― ± 10% supply pushing 6 leads to a drift of free running frequency 4 1.15 1.2 1.25 1.1 1.3 Supply Voltage (V) 2014/3/18 T. Siriburanon, Tokyo Tech
Issues of Conventional PMILFD (II) 10 Asymmetric Locking Range 5 Injection Power (dBm) 0 out+ -5 out- -10 M1 M2 in+ -15 in- Pbias=0.44 -20 M T1 Pbias=0.40 -25 V bias Pbias=0.36 -30 M T5 9 11 13 15 17 19 21 23 25 injection V bias Injection Frequency (GHz) Intrinsic free-running frequency of ILFD is sensitive to large injection signal 2014/3/18 T. Siriburanon, Tokyo Tech
Dual-Step Mixing using Direct Injection 11 secondary f out LPF 2f out primary f inj 2f out 4 f out f X2,X4,... Dual-step mixing mechanism for divide-by-4 and divide-by-6 operation 2014/3/18 T. Siriburanon, Tokyo Tech
Proposed ILFD Configuration 12 0 o 90 o 45 o 135 o 180 o 225 o 315 o 270 o 2 f o @ 0 o 2 f o @ 90 o 2 f o @ 180 o 2 f o @ 270 o -INJ +INJ I core I core I core I core Dual-Step Mixing with Second Harmonic Direct Injection 2014/3/18 T. Siriburanon, Tokyo Tech
Divide-by-4 Operation 13 Output Signal ~5GHz 2 nd Harmonic Output ~10GHz 4 th Harmonic Output ~20GHz Locked State of Divide-by-4 operation 2014/3/18 T. Siriburanon, Tokyo Tech
Divide-by-6 Operation 14 Output Signal ~5GHz 2 nd Harmonic Output ~10GHz 6 th Harmonic Output ~30GHz Locked State of Divide-by-6 operation 2014/3/18 T. Siriburanon, Tokyo Tech
Proposed Schematic 15 0 o 45 o 90 o 135 o 180 o 225 o 315 o 270 o I REF M inj2 M inj1 VDD V bias V bias R R Injection +OUT- Injection signal- signal+ IN- IN+ Secondary Mixer M4 M2 M3 M1 f out 2 f out f To even-harmonic enhanced node 2f out 4 f out f Schematic of the Proposed Dual-Step-Mixing ILFD using Even-Harmonic Direct Injection Technique
Chip Micrograph 16 Output signals 42 μ m 0.33mm 48 μ m ILFD Core Differential Injection Technology 65nm CMOS 0.002mm 2 Core area 2014/3/18 T. Siriburanon, Tokyo Tech
Experimental Results for divide-by-4 17 0 Injection Power (dBm) -2 -2 -4 -4 -6 -6 -8 -8 -10 -1 5.4mW 4.2mW -1 -12 3.6mW -14 -1 3.0mW -16 -1 14 14 16 16 18 18 20 20 22 22 24 24 26 26 Injection Frequency (GHz) Required frequency range for the 60-GHz wireless standards 2014/3/18 T. Siriburanon, Tokyo Tech
Divide-by-4 Performance Comparison 18 Locking Locking Div. Power FoM Area Features Range* Range* Ratio (mW) (%/mW) (mm 2 ) (GHz) (%) [4] Direct mixing 4 22.6-28 21 8.3 3.5 0.140 [5] Direct mixing 4 6.0-7.6 22 6.8 3.24 0.007 [6] Direct mixing 4 31.0-41.0 27 3.3 8.18 0.002 LC Direct [7] 4 58.5-72.9 21.9 2.2 9.95 0.032 mixing CML + LC [8] 4 13.5-30.5 77.3 7.3 10.6 0.33 ILFD Progressive [9]* 4 13.4-21.3 31 3.9 7.95 0.003 mixing Even- This harmonic- 4 15.2-20.4 24.25 3.1 7.82 0.002 enhanced FoM=(%Lock Range)/(mW Power) [4] A- SSCC’07 [5] RFIC’04 [6] ISSCC’06 [7] CICC’12 [8] MTT’11 [9] A- SSCC’11 2014/3/18 T. Siriburanon, Tokyo Tech
Experimental Results for divide-by-6 19 0 -2 -2 Injection Power (dBm) -4 -4 -6 -6 -8 -8 5.4mW 5.1mW -10 -1 4.2mW -1 -12 3.8mW 3.6mW -14 -1 3.0mW -1 -16 26 26 28 28 30 30 32 32 34 34 36 36 38 38 Injection Frequency (GHz) Required frequency range for the 60-GHz wireless standards 2014/3/18 T. Siriburanon, Tokyo Tech
Divide-by-6 Performance Comparison 20 Locking Div. Locking Power FoM Area Features Range* Ratio Range* (GHz) (mW) (%/mW) (mm 2 ) (%) [4] Direct mixing 3 21.7-24.9 13.7 8.3 1.7 0.140 [5] Direct mixing 3 53.9-57.8 7.0 4.6 1.5 0.800 [6] Direct mixing 6 141.0-144.3 2.7 14.0 0.2 1.160 [7] Direct mixing 6 10.2-11.3 11.0 6.8 1.6 0.007 [8] Direct mixing 6 14.6-15.4 5.0 12.5 0.4 0.300 Current [9] 6 121.0-124.8 3.5 4.5 0.8 0.140 reused ILFD Even- This harmonic- 6 27.7-32.0 13.2 3.1 4.0 0.002 enhanced FoM = (%Lock Range)/(mW Power) [4 ] MTT’12 [5 ] ISSCC’09 [6] A- SSCC’11 [ 7 ] RFIC’04 [8 ] RFIC’05 [9 ] MTT’13 2014/3/18 T. Siriburanon, Tokyo Tech
Frequency Drift over PVT variations 21 9 Frequency (GHz) Conventional 8 Measured Proposed 7 6 5 4 3 1.1 1.15 1.2 1.25 1.3 Supply Voltage (V) 6.5 7 Frequency (GHz) Frequency (GHz) Measured Measured 6 6 5.5 5 5 4 0 20 40 60 80 100 0 1 2 3 4 5 6 7 8 9 1011 Temperature (˚C) Chip number 2014/3/18
Integration with the 20GHz PLL 22 700um 20GHz 36MHz ref. VCO 2 Charge PFD LPF Pump 900um (54 54,55 55,56 56, , 5 ÷ 4 57 57,58 58,59 59,60 60) Proposed ILFD Proposed ILFD Proposed ILFD consumes only 4.2mW (Two cascading CML dividers consumes 14mW [1] ) [1] K. Okada, et al. , JSSC 2011 2014/3/18 T. Siriburanon, Tokyo Tech
Experimental Results 23 Channel 2 Channel 1 -20 -20 Phase noise (dBc/Hz) Phase noise (dBc/Hz) -40 -40 -60 -60 -80 -80 -100 -100 -120 -120 -140 -140 10K 100K 1M 10M 10K 100K 1M 10M Offset Frequency (Hz) Offset Frequency (Hz) Channel 3 Channel 4 -20 -20 Phase noise (dBc/Hz) Phase noise (dBc/Hz) -40 -40 -60 -60 -80 -80 -100 -100 -120 -120 -140 -140 10K 100K 1M 10M 10K 100K 1M 10M Offset Frequency (Hz) Offset Frequency (Hz) 2014/3/18
Conclusions 24 An Dual-Step-Mixing ILFD using a Even- Harmonic Direct Injection Technique is proposed for an enhanced locking range of divide-by-6 and divide-by-4 operations It achieves the widest locking range reported for divide-by-6 operation and comparable performance with the state-of-the-art divide-by- 4 ILFDs This work is suitable to be integrated in push- push or sub-harmonic injection-locked 60GHz PLLs 2014/3/18 T. Siriburanon, Tokyo Tech
25 Thank you for your interest
Acknowledgement 26 This work was partially supported by MIC, SCOPE, MEXT, STARC, Canon Foundation, and VDEC in collaboration with Cadence Design Systems, Inc., and Agilent Technologies Japan, Ltd.
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