Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications Paul Pop, Petru Eles, Zebo Peng, Viaceslav Izosimov Embedded Systems Lab (ESLAB) Linköping University, Sweden Magnus Hellring, Olof Bridal Dept. of Electronics and Software Volvo Technology Corp., Göteborg, Sweden 1/20 1 of 14
Heterogeneous Networks Distributed Heterogeneous System NoCs ... ... ... ... ... Factory Systems Heterogeneous Networks Multi-Cluster Systems Automotive Electronics 2/20 2 of 14
Distributed Safety-Critical Applications ... Applications distributed over � the heterogeneous networks � Reduce costs: use resources efficiently Gateway � Requirements: close to sensors/actuators ... Applications distributed over heterogeneous networks are difficult to... � � Analyze (guaranteeing timing constraints) [DATE’03] � Design (partitioning, mapping, This paper! bus access optimization) 3/20 3 of 14
Outline � Motivation � System architecture and application model � Scheduling for multi-clusters [DATE’03] � Design optimization problems � Partitioning � Mapping � Bus access optimization � Optimization strategy � Experimental results � Contributions and Message 4/20 4 of 14
Hardware Architecture Time-triggered cluster ... � Static cyclic scheduling � Time-triggered protocol Gateway ... Event-triggered cluster � Fixed priority preemptive scheduling � Controller area network protocol Time Triggered Protocol ( TTP ) Controller Area Network ( CAN ) Bus access scheme: � Priority bus, collision avoidance � time-division multiple-access (TDMA) Highest priority message � Schedule table located in each TTP � wins the contention controller: message descriptor list (MEDL) Priorities encoded in the frame identifier � S 0 S 1 S 2 S G S 0 S 1 S 2 S G Slot TDMA Round Cycle of two rounds 5/20 5 of 14
... Software Architecture ... Gateway Time-triggered cluster N G N 2 CAN Controller N 1 CPU CPU CPU CPU CAN Controller P 1 P 4 m 3 Out CAN Out TTP Out N2 T T m 1 m 1 m 2 m 3 MBI P 2 P 3 MBI TTP Controller TTP Controller Event-triggered cluster S G S 1 S G S 1 Round2 6/20 6 of 14
Multi-Cluster Scheduling [DATE’03] Application, Partitioning, TT Bus Mapping , Configuration Priorities Architecture Response Response Times Static Time Scheduling Analysis Offsets Multi-Cluster Scheduling Schedule Response Tables times � MultiClusterScheduling algorithm � Schedulability analysis: communication delays through the gateway � Scheduling: cannot be addressed separately for each cluster 7/20 7 of 14
Problem Formulation � Input � System architecture � Application � Partial partitioning and mapping, based on the designer’s experience � Output � Design implementation ... such that the application is schedulable � Partitioning for each un-partitioned process Partitioning and ... � Mapping for each un-mapped process mapping � Priorities for ET messages Communication Application : set of process graphs � TDMA slot sequence and sizes for the TT bus Architecture : Multi-cluster infrastructure � Priorities for ET processes Scheduling � Schedule table for TT messages information 8/20 8 of 14
Motivational Example #1/1 In which cluster to place process P 4 ? Deadline Deadline for P 5 for P 6 N 1 P 1 (faster) N 2 Met P 4 P 3 P 6 (slower) N 3 Missed P 2 P 5 CAN N 1 N 2 N 3 P 1 P 2 TTC ETC P 1 70 X X N 1 N 2 N 3 P 2 X X 40 P 3 X 50 X P 3 P 4 P 4 X 70 90 P 5 X X 40 TTP P 6 X 40 X P 5 P 6 9/20 9 of 14
Motivational Example #1/2 In which cluster to place process P 4 ? Deadline Deadline for P 5 for P 6 Preemption N 1 N 1 P 1 P 1 not allowed (faster) N 2 (faster) N 2 Met Met P 4 P 4 P 3 P 3 P 4 P 6 P 6 (slower) N 3 (slower) N 3 Preempted Missed Met P 2 P 2 P 5 P 5 CAN N 1 N 2 N 3 P 1 P 2 TTC ETC P 1 70 X X N 1 N 2 N 3 P 2 X X 40 P 3 X 50 X P 3 P 4 P 4 X 70 90 P 5 X X 40 TTP P 6 X 40 X P 5 P 6 10/20 10 of 14
Motivational Example #1/3 In which cluster to place process P 4 ? Deadline Deadline for P 5 for P 6 Preemption N 1 N 1 N 1 P 1 P 1 P 1 not allowed (faster) N 2 (faster) N 2 (faster) N 2 Met Met Met P 4 P 4 P 3 P 3 P 4 P 3 P 6 P 6 P 6 Met (slower) N 3 (slower) N 3 (slower) N 3 Preempted Missed Met P 2 P 2 P 2 P 4 P 5 P 5 P 4 P 5 Preempted CAN N 1 N 2 N 3 P 1 P 2 TTC ETC P 1 70 X X N 1 N 2 N 3 P 2 X X 40 P 3 X 50 X P 3 P 4 P 4 X 70 90 P 5 X X 40 TTP P 6 X 40 X P 5 P 6 11/20 11 of 14
Motivational Example #2/1 Where to map process P 2 ? Deadline N 3 Missed P 3 N 2 P 2 N 1 P 1 m 1 TTP m 2 S 2 S 3 S G S 2 S 3 S 1 S G S 3 S 1 S G N G CAN N 4 CAN TTC ETC N 1 N 2 N 3 N 4 N 1 N 2 N 3 N 4 m 1 m 2 N G P 1 20 X X X P 1 P 2 P 3 P 2 X 40 X 50 P 3 X X 20 X TTP 12/20 12 of 14
Motivational Example #2/2 Where to map process P 2 ? Deadline N 3 N 3 Met Missed P 3 P 3 N 2 N 2 P 2 N 1 N 1 P 1 P 1 m 1 m 1 TTP TTP m 2 m 2 S 2 S 2 S 3 S 2 S G S G S 2 S 2 S 3 S 3 S 1 S 1 S G S 2 S 3 S 3 S 1 S 1 S G S G N G N G T T m 1 CAN CAN m 2 N 4 N 4 N 4 P 2 CAN TTC ETC N 1 N 2 N 3 N 4 N 1 N 2 N 3 N 4 m 1 m 2 N G P 1 20 X X X P 1 P 2 P 3 P 2 X 40 X 50 P 3 X X 20 X TTP 13/20 13 of 14
Motivational Example #3/1 What are the priorities on ETC? Which slot should come first on the TTC? Deadline N 1 Missed P 1 P 4 Round 4 TTP S 1 S G m 1 S G m 2 S G S 1 m 3 S 1 m 4 S 1 S G N G T T T T CAN m 1 m 3 m 2 m 4 N 2 P 2 P 3 CAN P 1 N 1 N 2 m 1 m 2 TTC ETC P 1 20 X N 1 N 2 P 2 X 40 P 2 P 3 P 3 X 20 m 3 m 4 P 4 40 X P 4 TTP 14/20 14 of 14
Motivational Example #3/2 What are the priorities on ETC? Which slot should come first on the TTC? Deadline N 1 N 1 Missed Missed P 1 P 1 P 4 P 4 Round 4 TTP TTP S 1 S 1 S G S G m 1 m 1 S G S G m 2 m 2 S G S G S 1 S 1 m 3 m 3 m 4 S 1 S 1 m 4 S G S 1 S G N G N G T T T T T T T T CAN CAN m 1 m 1 m 3 m 2 m 2 m 3 m 4 m 4 N 2 N 2 P 2 P 2 P 3 P 3 CAN P 1 N 1 N 2 m 1 m 2 TTC ETC P 1 20 X N 1 N 2 P 2 X 40 P 2 P 3 P 3 X 20 m 3 m 4 P 4 40 X P 4 TTP 15/20 15 of 14
Motivational Example #3/3 What are the priorities on ETC? Which slot should come first on the TTC? Deadline N 1 N 1 N 1 Missed Met Missed P 1 P 1 P 1 P 4 P 4 P 4 Round 4 TTP TTP TTP S 1 S 1 S G m 1 m 2 S G S G m 1 m 1 S G S G S G S 1 m 2 m 2 m 4 S G S G S 1 m 3 S 1 S 1 m 3 m 3 m 4 S 1 S 1 S G S 1 m 4 S G S 1 S G Round 1 N G N G N G T T T T T T T T T T T CAN CAN CAN m 2 m 1 m 1 m 1 m 4 m 3 m 2 m 3 m 3 m 2 m 4 m 4 N 2 N 2 N 2 P 3 P 2 P 2 P 2 P 3 P 3 CAN P 1 N 1 N 2 m 1 m 2 TTC ETC P 1 20 X N 1 N 2 P 2 X 40 P 2 P 3 P 3 X 20 m 3 m 4 P 4 40 X P 4 TTP 16/20 16 of 14
Optimization Strategy Multi-Cluster Configuration � 1. Initial Partitioninig and Mapping Determines an initial partitioning and mapping � List scheduling-based greedy approach � Priority of ready processes: critical path � 2. Partitioning and Mapping Heuristic Iteratively improves on the initial partitioning and mapping � Intelligent design transformations that improve schedulability � Based on feedback from MultiClusterScheduling � 3. Bus Access Optimization Determines the slot sequence and lengths on the TTC, � message priorities on the ETC Greedy optimization heuristic � Straightforward solution � Partitioning and mapping that balances the utilization of processors and buses � Could be produced by a designer without optimzation tools � 17/20 17 of 14
Experimental Results Can we increase the number of schedulable applications? Percentage schedulable applications [%] 100% 90% 80% 70% Bus Access 60% Optimization 50% Partitioning and 40% Mapping Heuristic 30% Initial Partitioning 20% and Mapping 10% Straightforward 0% solution 50 100 150 200 250 Number of processes 18/20 18 of 14
Experimental Results, Cont. How time-consuming is our optimization strategy? 5:20 Average execution time [hours:minutes] Multi-Cluster 5:00 Configuration 4:40 4:20 4:00 3:40 Partitioning and 3:20 Mapping Heuristic 3:00 2:40 2:20 2:00 1:40 Initial Partitioning 1:20 and Mapping 1:00 0:40 Bus Access 0:20 Optimization 0:00 50 100 150 200 250 Number of processes 19/20 19 of 14
Contributions and Message � Contributions � Addressed design problems characteristic to multi-clusters � Partitioning � Mapping � Bus Access Optimization � Proposed heuristics for design optimization Analysis and optimization methods are needed for the efficient implementation of applications distributed over interconnected heterogeneous networks . 20/20 20 of 14
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