Florence KTH, Stockholm Trieste Rome CNR, Florence Siegen Naples Data Acquisition System of the PAMELA Experiment Alessandro Basili INFN Roma II, Università di Roma “Tor Vergata”
Presentation Overview 1) The acquisition strategy: system requirements and constraints data reduction solution trigger-busy mechanism 2) System details: Interface Data Acquisition board (IDAQ) Pamela Storage and Control Unit (PSCU) 3) Related topics: software organization housekeeping
Requirements & constraints Trigger rate estimation: - S1 x S2 x S3 12 Hz / G.F. = 20.5 cm 2 sr Packet size per event: 6 KBytes (roughly), more then 40,000 analog channels � 6 downloads per day � 200 seconds connection 6 GByte per day � speed rate of 12 MBps
Data reduction solution Trigger board � Front end boards Tracker A/D � DSP boards DSP DSP A/D � Trigger board Calorimeter � IDAQ board A/D DSP � PSCU DSP A/D Tof A/D DSP DSP PSCU IDAQ A/D IDAQ AC A/D DSP DSP A/D A/D ND A/D S4
Trigger-busy mechanism S1 � Trigger board sends trigger to every one, only if the idaq busy signal is S2 released. � Idaq starts in busy condition. � Only at the end of settings S3 configurations will be sent a “release busy” command busy Power on Idaq Trigger trigger Trigger delivered Trigger vetoed PSCU
PSCU-IDAQ protocol - Trigger mode 1) Settings before the acquisition: - initialization - Command queue selection - calibration 2) DMA arming: - Data timeout and Event timeout fixed - Event header written in the Ram 3) Acquisition runs: cycled reloading of the command queue Important: the cpu time consuming is very low; the acquisition is managed by the IDAQ (no interrupt handling)
Event acquisition overview 1) Pamela starts up: the Idaq is busy PSCU 2) First command is sent: RELEASE BUSY Not busy 3) First trigger comes and Idaq goes again in IDAQ “busy” state. 4) The read commands are hanging on because idaq will release the acknoledge to the PIF only after 3.5 ms from the trigger 5) All the “read event” commands are sent to FE FE FE all subdetectors 6) Once the whole data are stored in PIF Ram, the “DATA TIMEOUT” interrupt will tell the cpu that the acquisition has finished.
Event acquisition overview Vetoed triggers Idaq trigger Idaq busy cmd strb cmd ack daq strb daq ack Commands 3.5 ms timeout: for compression algorithm to DSP boards Answers from DSP boards
IDAQ : interface data acquisition RESET ADSP2187 TRIGG RS BUSY LVDS 422 ALARM DSP controller e RS checker PM & DM OUT-Buffers 422 TX Mux LVDS TTL 1 in - 14 out CMD Buffer TTL LVDS MAIN controller e Async interfaces multiplexer Status & PWR DAQ Buffer TTL LVDS RX Mux IN-Buffers 14 in - 1 out LVDS TTL FLASH CTRL con RAM CTRL con Hamming codec Hamming codec FLASH FLASH SRAM SRAM 1Mx8 1Mx8 512Kx8 512Kx8
IDAQ : interface data acquisition Ram controller clk_tx A[17..0] tx D[7..0] end_tx DEC_CMD AR[17..0] RAMSERCLK SERIAL DR[7..0] rx Interface HAMMING BHE end_cmd OEN RAM RAMRES WEN Interface cmd_nda CEN BLE WERN MCLK OERN CERN cmd_err BHER RAM_ERR BLER
IDAQ : interface data acquisition Flash controller clk_tx AH [19..0] tx DH [7..0] end_tx DEC_CMD AL [19..0] FLASHSERCLK SERIAL DL [7..0] rx Interface HAMMING RYBYN_H end_cmd OEN_H FLASH FLASHRES WEN_H Interface CEN_H RESETN_H RYBYN_L MCLK OEN_L WEN_L cmd_err CEN_L Hamm_err RESETN_L busy
IDAQ : interface data acquisition DSP controller nIS clk_tx nIWR tx nIAL end_tx nIRD DSPSERCLK nIAD [15..0] rx nIACK end_cmd IDMA nRESET cmd_nda SERIAL Interface DEC_CMD nIRQL0 Interface nPWD DSPRES FL0 MCLK FL1 checking FL2 dsp_err CLKIN cmd_err dat_err mode [3..0] busy PF4 PF6 PF7
PSCU 1553 MIL STD CMD DAT TAM TM TC HKU CPU PIF PCMCIA BUS Sys BUS W BUS R BUS 32 32 DC/DC Mem Mod
CPU module 1) Processor SPARC32 V7 17 Mips @24 MHz 2) SRAM 1M x 32 EDAC protected JTAG provided 3) Boot PROM
CPU module 4) EEPROM 256K x 32 EDAC protected 5) MIL-STD 1553 Bus Controller/Remote Terminal Function with 64K x 16 Ram buffer 6) CRIMEA: glue logic for PCMCIA bus controller, parallel S-90 bus interface
SSMM module 1) Eleven indipendent memory columns 2) Each column is composed by 4 Memory Cubes 3) Each Cube is 8 x 8 MB chip SDRAM 4) Eleven indipendent Current Limiter for Latch-up protection 5) DRAMMA: Asic for DRAM managing 8 modules for data storage, 2 for Reed- Solomon Check Symbols and 1 for local redundancy
PIF module FPGA based interface (ALVARO): 1) CMD DMA management 2) DAQ DMA management 3) MM Parallel W/R bus management 4) TAM DMA management 5) 1 programmable Event Timeout 6) 1 programmable Data Timeout
HKU module House keeping unit: FPGA based interface commands 1) 2 serial links RS422 2) 24 High voltage commands (26 V) 3) 2 Differential Bi-level commands acquisitions 1) 32 Contact closures 2) 8 Bi-level acquisition 3) 4 Differential Bi-level acquisition 4) 16 Analog double ended acquisition 5) 16 Analog double ended thermistors 6) 2 Serial Digital 16 bits acquisition
Considerations and conclusions Considerations: 1) A lot more about housekeeping 2) Redundancy and SEU & SEL protection 3) Software organization 4) Power system Conclusions: 1) Make it simple 2) Strong debug 3) HOPE IT WORKS!!!
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