1 CSCI 350 Ch. 8 – Address Translation Mark Redekopp Michael Shindler & Ramesh Govindan
2 Abstracting Memory • Thread = Abstraction of the processor • What about abstracting memory? – "All problems in computer science can be solved by another level of indirection" • Address translation => Abstraction of memory Processor Data Input Output Memory Devices Devices Software Program
3 Benefits of Address Translation • What is enabled through address translation? – Illusion of more or less memory than physically present – Isolation – Controlled sharing of code or data – Efficient I/O (memory-mapped files) – Dynamic allocation (Heap / Stack growth) – Process migration
4 Virtual vs. Physical Addresses Pg. 0 Pg. 1 Pg. 2 0xffffffff • Translation between: Pg. 3 I/O Pg. 0 and unused Pg. 1 un- … – Virtual address: Address used Pg. 2 area Pg. 3 used by the process Pg. 0 0x3fffffff frame Pg. 1 Pg. 0 (programmer) Pg. 1 Pg. 2 Pg. 1 Pg. 0 unused – Physical address: Physical Pg. 2 Pg. 3 unused memory location of the Pg. 2 … Pg. 0 Pg. 0 Pg. 1 desired data Pg. 2 Pg. 0 frame 0x00000000 Pg. 3 Pg. 1 Pg. 2 Physical Pg. 3 Memory and unused Secondary Address Space … Storage Virtual Physical Translation Unit / Fictitious Virtual Addr Proc. Addr Memory MMU Address Spaces Core (Mem. Mgmt. Unit) Data
5 Translation Goals & Roadmap • Functional Goals – Isolation and transparency to programmer – Controlled sharing – Support for sparse address spaces and dynamic resizing • Performance Goals – Flexible physical placement – Fast translation – Low memory overhead (compact tables) • We'll first focus on function and then discuss efficiency
6 Evolution of Translation • Base + bounds check • Segmentation • Paging
7 SEGMENTATION
8 Base and Bounds • Each running process has a: – Virtual address space from VA: 0 to N-1 – Physical address space from PA: BASE to BASE+N-1 • Program written (compiled) using VAs and determine necessary BOUND (i.e. N) • When loaded, OS assigns BASE (phys. addr. space) dynamically • Hardware converts VAs to PAs and performs bounds check P2 Phys Addr. base Space Physical Addr eax 0x14000 • The "BASE" and "BOUNDS" registers PA: 0x16000 esp unused and checking hardware are termed Base + Bound: + 0x19000 the MMU (Mem. Mgmt. Unit) or ebx P1 Phys. VA: 0x02000 > Exception Translation Unit Addr. Virtual Addr bound eip 0x16000 • Base and Bound are loaded/restored Space 0x05000 on process switches. Translation Unit / MMU CPU Base: 0x14000
9 Base and Bounds Pros & Cons • Pros: – Simple – Provides isolation amongst processes • Cons: – No easy way to share data – Can't enforce access rights within the process (e.g. code = read only) • Processes can "rewrite" their own address space P2 Phys Addr. base Space Physical Addr eax 0x14000 • The "BASE" and "BOUNDS" registers PA: 0x16000 esp unused and checking hardware are termed Base + Bound: + 0x19000 the MMU (Mem. Mgmt. Unit) or ebx P1 Phys. VA: 0x02000 > Exception Translation Unit Addr. Virtual Addr bound eip 0x16000 • Base and Bound are loaded/restored Space 0x05000 on process switches. Translation Unit / MMU CPU Base: 0x14000
10 Segmentation • Allow a process to be broken into multiple base + bounds "segments" – Code, data, stack, heap • Multiple base + bounds registers stored in a table unused in the MMU • Updating the table is a "privileged" (kernel-only) Base + Bound: Data 0x2d200 Seg. operation Base: 0x2a000 Bound R/W Base Base + Bound: Stack 0x19000 Descriptor 0 0x2a000 0x03200 R/W Physical Addr Seg. eax Table 0x14000 0x05000 R/W 1 PA: 0x16000 esp 2 0x0400 R 0x08000 0x16000 ebx VA: 0x102000 1 02000 Base: 0x14000 + eip seg. offset Virtual Addr Base + Bound: > Exception Code 1:1:3 ss 0x80400 Seg. Translation Unit / MMU CPU Base: 0x08000 Seg. Reg. 13 bits=Seg. 1=LDT/0=GDT 0-3=RPL Format: http://ece-research.unm.edu/jimp/310/slides/micro_arch2.html
11 Segmentation Pros • Enforce access rights to various segment using access bit entries in the segment descriptor • Detect out of bounds accesses (segmentation fault) • Memory mapped files (segment = file on disk) • Sharing code + data (see example in a few slides) unused – Shared code / libraries and/or data – One code segment for multiple instances of a running program Base + Bound: Data • Key idea: What is behind a segment can be "anything" 0x2d200 Seg. – Translation gives us a chance to intervene Base: 0x2a000 Base + Bound: Stack Bound R/W Base 0x19000 Seg. Descriptor 0 0x2a000 0x03200 R/W Physical Addr eax Table 0x14000 0x05000 R/W 1 PA: 0x16000 esp 0x16000 2 0x0400 R 0x08000 ebx Base: 0x14000 VA: 0x102000 1 02000 + eip seg. offset Base + Bound: Code Virtual Addr > 0x80400 Exception Seg. 1:1:3 ss Translation Unit / MMU CPU Base: 0x08000
12 Segmentation Cons • External Fragmentation – As a system runs and segments are created and deleted the physical address may have many small, unusable gaps and we effectively lose that memory for use unused • Growing a segment may be hard since they must be contiguous (other segments may be bracketing Base + Bound: Data our growth) 0x2d200 Seg. Base: 0x2a000 Bound R/W Base Base + Bound: Stack 0x19000 Descriptor 0 0x2a000 0x03200 R/W Physical Addr Seg. eax Table 0x14000 0x05000 R/W 1 PA: 0x16000 esp 2 0x0400 R 0x08000 0x16000 ebx VA: 0x102000 1 02000 Base: 0x14000 + eip seg. offset Virtual Addr Base + Bound: > Exception Code 1:1:3 ss 0x80400 Seg. Translation Unit / MMU CPU Base: 0x08000 Seg. Reg. 13 bits=Seg. 1=LDT/0=GDT 0-3=RPL Format: http://ece-research.unm.edu/jimp/310/slides/micro_arch2.html
13 x86 Segmentation • Segment descriptors are stored in tables in the kernel's memory region • Local descriptor table (LDT) [Mem] : Up to 8192 segment GDT unused descriptors for each process 0xc4000 • 8191 Global descriptor table (GDT) [Mem] : Kernel, LDT, and a few LDT1 other types of descriptors 0xc0000 0 – Pointed to by GDTR / Interrupt descriptor table pointed to by IDTR Base + Bound: Data • MMU (in CPU) stores a cache of descriptors from the process' 0x2d200 Seg. LDT for each segment register (CS, DS, SS, ES, FS, GS) Base: 0x2a000 eax Descriptor Cache Bound R/W Base Base + Bound: 0xc4000 GDTR Stack 0x19000 esp DS 0x2a000 0x03200 R/W Seg. IDTR 0x14000 0x05000 R/W SS ebx LDT/ VA: 0x102000 0xc0000 CS 0x0400 R 0x08000 TR eip 0x16000 1 02000 Base: 0x14000 + 1:1:3 seg. offset ss PA: 0x16000 Virtual Addr 0:1:3 Base + Bound: > Exception cs Code Physical Addr 0x80400 2:1:3 Seg. ds Translation Unit / MMU CPU Base: 0x08000 http://ece-research.unm.edu/jimp/310/slides/micro_arch2.html
14 Multiple Processes + Sharing 8191 LDT2 • A physical segment can be shared by 2 0 processes by setting up the descriptor GDT unused 0xc4000 8191 LDT1 0xc0000 0 Base Bound R/W P2 DS 0x01000 R/W 0x7e000 Process 2 Data Base: 0x7e000 0x6e000 0x05000 R/W SS CS 0x08000 0x0400 R P1 Data Base: 0x7a000 eax Descriptor Cache Bound R/W Base Process 1 0xc4000 GDTR esp DS 0x7a000 0x03200 R/W P2 IDTR 0x14000 0x05000 R/W SS ebx Stack LDT/ Base: 0x6e000 VA: 0x102000 0xc0000 CS 0x0400 R 0x08000 TR eip P1 1 02000 Stack + 1:1:3 seg. offset ss 0x16000 PA: 0x16000 Virtual Addr 0:1:3 > Exception cs Base: 0x14000 Physical Addr 2:1:3 ds P1/P2 Translation Unit / MMU CPU Code Base: 0x08000 http://ece-research.unm.edu/jimp/310/slides/micro_arch2.html
15 Forking a Process & Copy-On-Write • Recall forking a process makes a "copy" of the address space – Generally going to "exec" soon afterward • In reality we can just make a copy of the page directory but mark all entries read/only unused • On any write, we will gen. an exception and we can make a copy of the segment for the child (aka Copy-On-Write) • If no write, the two processes can share and thus we save time Base + Bound: Data avoiding the copy 0x2d200 Seg. • This is an example of a general concept called Lazy Evaluation Base: 0x2a000 – Start by doing minimal required work; do more work when required Base + Bound: Stack 0x19000 Seg. Bound R/W Base Parent Proc Seg. 0 0x2a000 0x03200 R /W eax Table 0x14000 0x05000 R /W 1 0x16000 esp (Read only) 2 0x0400 R 0x08000 Base: 0x14000 ebx VA: 0x102000 Forked Proc Seg. 0 0x2a000 0x03200 R Base + Bound: Code eip Table 0x80400 0x14000 0x05000 R 1 Seg. (Read only) 2 0x0400 R 0x08000 1:1:3 ss Base: 0x08000 Translation Unit / MMU CPU
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