Correction in the LTE Downlink Receiver Elliot Briggs 1 , Chunmei - PowerPoint PPT Presentation

Sample Clock Offset Detection and Correction in the LTE Downlink Receiver Elliot Briggs 1 , Chunmei Kang 2 , Amit Mane 2 , Dan McLane 2 , Brian Nutter 1 SDR’11 - WinnComm Europe Brussels, Belgium June 22 nd – 24 th 1: Texas Tech University, 2: Innovative Integration

Presentation Overview • OFDM Receiver Synchronization Basics • Mechanics of Sample Clock Offset • Sample Clock Offset Detection • Developed Sample Clock Correction Technique • Results 1

OFDM Receiver Synchronization Basics Traditional OFDM model example: Remove CP Add CP Signal Impairments Parallel to Serial Serial to Parallel Single/Multiple Complex symbols path delay Complex symbols D/A A/D channel IDFT DFT … … … … RX TX * Sample ~ Sample clock clock Freq. offset WGN Impairments: • AWGN: weak (noisy) signal • Frequency shift: errors in RF electronics (TX and RX) • Delay: Asynchronous startup time, multiple paths • Sample Clock Offset? 2

OFDM Receiver Synchronization Basics Ideal Orthogonal Reception 1 Ideal OFDM Reception: 0.8 •The receiver’s FFT bins are aligned with each subcarrier 0.6 • Here, at the receiver, each 0.4 subcarrier is orthogonal to the others 0.2 0 -0.2 -0.4 -4 -3 -2 -1 0 1 2 3 4 FFT bin center positions at the Receiver (subcarrier index) 3

OFDM Receiver Synchronization Basics Reception with ICI from 20% Frequency Shift 1 OFDM Reception Affected by Frequency shift: 0.8 • Each FFT bin is misaligned by 0.6 an equal amount 0.4 • Each received subcarrier experiences the same amount 0.2 of ICI 0 -0.2 -0.4 -4 -3 -2 -1 0 1 2 3 4 FFT bin center positions at the Receiver (subcarrier index) 4

OFDM Receiver Synchronization Basics Reception with ICI from 5% Sample Clock Offset 1 OFDM Reception Affected by Sample Clock Offset: 0.8 • Each FFT bin has a 0.6 cumulative amount of shift 0.4 • The outer subcarrier positions experience the most ICI 0.2 0 -0.2 -0.4 -4 -3 -2 -1 0 1 2 3 4 FFT bin center positions at the Receiver (subcarrier index) 5

OFDM Receiver Synchronization Basics LTE signal with 1,229 Hz sample clock offset at the receiver (40ppm total) • 40 ppm error at the receiver 1.2 simulates the maximum error from 20 ppm clock oscillators at the 1 transmitter and receiver normalized magnitude 0.8 • 40ppm = 1.229 kHz , 8.2% of one subcarrier spacing 0.6 • Here, the SNR is 50 dB before the 0.4 sampling clock error is added 0.2 0 0 256 512 768 1024 1280 1536 1792 2048 subcarrier index 6

OFDM Receiver Synchronization Basics LTE signal with 1,229 Hz sample clock offset at the receiver (40ppm total) LTE signal with 1,229 Hz sample clock offset at the receiver (40ppm total) 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 imaginary imaginary 0 0 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 real real • A slight phase shift occurs from • After the phase is unwound, fractional timing offset only the ICI component remains • The outer subcarrier positions • The ICI appears as noise at the are no longer orthogonal and outer subcarrier locations contain energy from neighboring subcarriers 7

OFDM Receiver Synchronization Basics SNR Degradation vs. Subcarrier Index at Es/No = 50 dB 18 • ICI causes SNR degradation 1 ppm 16 5 ppm which is the most severe at the 10 ppm 14 outer subcarrier locations. 20 ppm 12 degradation (dB) • Even a 5ppm sample clock error 10 can cause 6 dB of degradation 8 when Es/No = 50 dB 6 4 1 E 2 6 s [1] D 10 log 1 n 10 f n 10 s 3 N 2 o 0 1 200 400 600 800 1000 1200 subcarrier index 8

OFDM Receiver Synchronization Basics SNR Degradation vs. SCO at Varying Es/No (subcarrier index = 1200) 2 10 • The level of degradation is displayed for several levels of SNR 1 10 degradation (dB) • The SNR is adversely affected, even with modest clock offsets 0 10 20 dB 30 dB 40 dB -1 10 50 dB 5 10 15 20 25 30 35 40 clock offset (ppm) 9

Mechanics of Sample Clock Offset Transmitted OFDM symbols: symbol duration Cyclic prefix duration … … CP CP CP time T 1 30 . 72 MHz LTE Example: s N 512 • “Extended” cyclic prefix mode [2] CP • 20 MHz mode N 2048 FFT • Ideally, each symbol lasts only 83.33 μ s μs T N N T 83 . 33 symbol CP FFT s 10

Mechanics of Sample Clock Offset Received OFDM symbols: … … perfect sample clock CP CP CP frequency: … … sample clock frequency CP CP CP is too fast: … … sample clock frequency CP CP CP is too slow: sampled time • 2560 samples will take a longer or shorter amount T 1 30 . 72 MHz 1 / f s error of time for the receiver to collect, depending on the μs T N N T 83 . 33 offset conditions symbol CP FFT s • The rate that the symbols drift from the perfect case directly indicates the sampling clock offset magnitude. • The direction in which the symbols drift indicate the sampling clock offset direction 11

Sample Clock Offset Detection Any DFT-based OFDM system must have an FFT window timing synchronization component to properly align the FFT window FFT window t-2 FFT window t-1 FFT window t … … CP CP CP time Any FFT timing synchronization method can give sample clock offset information • Using the LTE Primary Synchronization Signal (PSS) o Timing information provided every 5 ms • Cyclic Prefix Correlation o Timing information provided every 83.33 μ s 12

Sample Clock Offset Detection Example: (-)+100 Hz clock offset error: • Generates (removes) 100 extra samples per second. • This will generate (remove) 1 sample for after 120 OFDM symbols, or 0.0083 samples to each symbol • A +12 kHz clock offset will generate an entire sample for each OFDM symbol N 12 , 000 [ ] [ ] [ 1 ] f n S n t S n t error offset offset N 1 t 13

Sample Clock Offset Detection Symbol Start Location with Respect to the RX Clock (600 Hz SCO @ RX) 2500 4 timing drift distribution x 10 12 2000 10 symbol start sample index 8 1500 frequency 6 1000 4 2 500 0 -2 -1 0 1 2 symbol-to-symbol timing offset difference 0 0 2 4 6 8 10 12 14 . 05 symbol index 4 x 10 n N 135 , 000 N 12 , 000 f [ n ] S [ n t ] S [ n t 1 ] 12 , 000 . 05 600 Hz error offset offset N t 1 14

Sample Clock Offset Detection Fractional Delay Modulation to Compensate a 600 Hz SC Error • SCO can be corrected if the signal is 1 resampled at the correct sampling rate 0.9 0.8 fractional delay (fractional samples) • Modulate the fractional delay value at 0.7 every sample to effectively resample the 0.6 signal 0.5 • When the fractional delay value 0.4 Underflow Underflow over/underflows, repeat/skip a sample 0.3 0.2 0.1 0 0 5 10 15 20 25 30 35 40 OFDM Symbol Index 15

Developed Sample Clock Correction Technique Fractional Delay Modulation to Compensate a 600 Hz SC Error • In this example, each sample has a 1 -.05/2560 delay difference from the 0.9 previous sample to correct the .05/2560 0.8 fractional delay (fractional samples) from the sample clock offset. 0.7 0.6 • When a negative delay is requested, a 0.5 sample is skipped. 0.4 Underflow Underflow • Here, fewer samples are produced at 0.3 the output of the resampling filter than 0.2 are input 0.1 0 • Ideally, the resampler produces 2560 0 5 10 15 20 25 30 35 40 OFDM Symbol Index samples per 83.33 μ s The resampler “compresses” the signal by continuously reducing the delay for each sample • The signal should have stationary symbol timing after resampling 1 16

Developed Sample Clock Correction Technique • The ML timing and frequency offset estimator [3] uses the cyclic prefix o The timing estimate is used by the loop filter and to trigger an FFT conversion o The frequency offset estimate is used to correct residual frequency shift 1 17

Developed Sample Clock Correction Technique • The receiver uses feedback correction to adjust the symbol timing and frequency correction • The timing loop filter averages many timing estimates to get an average window drift rate, just as in the previous example • The delay accumulator constantly accumulates fractional delay and modulates a fractional resampling filter 18

FPGA Hardware Implementation Results • Design implemented in an FPGA Hardware Results - 40 ppm SCO compensation performance 40 X5-400M FPGA board by perfect reception, no SCO 38 Innovative Integration 40 ppm SCO, no compensation 40 ppm SCO, with compensation 36 • Two separate clocks are 34 measured effective Es/No (dB) used, the frequency difference 32 is measured 30 28 • With SCO compensation 26 enabled, the minimum SNR gain is around 3 dB 24 22 • SNR gains increase at higher 20 values of Es/No (~ 6 dB)! 18 16 22 24 26 28 30 32 34 36 38 40 channel Es/No (dB) 1 19