correct by design control synthesis for multilevel
play

Correct-by-Design Control Synthesis for Multilevel Converters using - PowerPoint PPT Presentation

Sep 10, 2023 •110 likes •1.22k views

Correct-by-Design Control Synthesis for Multilevel Converters using State Space Decomposition G. Feld 2 L. Fribourg 1 D. Labrousse 2 B. Revol 2 R. Soulat 1 1 LSV, 2 SATIE - ENS Cachan & CNRS FSFMA, 13 May 2014 G. Feld 2 , L. Fribourg 1 , D.

  1. Context: Multilevel Converters Principle of Multilevel Converters made of capacitors and pairs of (complementary) switching cells G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 7 / 34

  2. Context: Multilevel Converters Principle of Multilevel Converters made of capacitors and pairs of (complementary) switching cells two source of input voltages G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 7 / 34

  3. Context: Multilevel Converters Principle of Multilevel Converters made of capacitors and pairs of (complementary) switching cells two source of input voltages according to the positions of the cells (mode), one is able to fraction the load voltage G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 7 / 34

  4. Context: Multilevel Converters Principle of Multilevel Converters made of capacitors and pairs of (complementary) switching cells two source of input voltages according to the positions of the cells (mode), one is able to fraction the load voltage switching of modes occur periodically (sampling time τ ) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 7 / 34

  5. Context: Multilevel Converters Principle of Multilevel Converters made of capacitors and pairs of (complementary) switching cells two source of input voltages according to the positions of the cells (mode), one is able to fraction the load voltage switching of modes occur periodically (sampling time τ ) � transform a DC voltage into a staircase waveform ( ≈ sinusoidal) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 7 / 34

  6. Context: Multilevel Converters Focus According to the position of S i and S i +1 , the capacitor C i contributes or not to the output voltage. G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 8 / 34

  7. Context: Multilevel Converters Focus According to the position of S i and S i +1 , the capacitor C i contributes or not to the output voltage. By global positioning of the switching cells, one is thus able to fraction the output voltage between − v i and + v i . G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 8 / 34

  8. Context: Multilevel Converters Example: 5-level converter By controlling the modes at each sampling time, one can synthesize a 5-level staircase function G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 9 / 34

  9. Context: Multilevel Converters Example: 5-level converter By controlling the modes at each sampling time, one can synthesize a 5-level staircase function G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 9 / 34

  10. Context: Multilevel Converters Example: 5-level converter By controlling the modes at each sampling time, one can synthesize a 5-level staircase function G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 9 / 34

  11. Context: Multilevel Converters Example: 5-level converter By controlling the modes at each sampling time, one can synthesize a 5-level staircase function G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 9 / 34

  12. Context: Multilevel Converters Example: 5-level converter By controlling the modes at each sampling time, one can synthesize a 5-level staircase function G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 9 / 34

  13. Context: Multilevel Converters Example: 5-level converter By controlling the modes at each sampling time, one can synthesize a 5-level staircase function G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 9 / 34

  14. Context: Multilevel Converters Example: 5-level converter By controlling the modes at each sampling time, one can synthesize a 5-level staircase function G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 9 / 34

  15. Context: Multilevel Converters Example : 5-level multilevel converter A priori, many switching sequences exist: paths of a graph where nodes correspond to modes ( S 1 S 2 S 3 S 4 ) with S i = 0 , 1, and adjacent nodes differ by one bit G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 10 / 34

  16. Context: Multilevel Converters Example : 5-level multilevel converter A priori, many switching sequences exist: paths of a graph where nodes correspond to modes ( S 1 S 2 S 3 S 4 ) with S i = 0 , 1, and adjacent nodes differ by one bit G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 10 / 34

  17. Context: Multilevel Converters Example : 5-level multilevel converter A priori, many switching sequences exist: paths of a graph where nodes correspond to modes ( S 1 S 2 S 3 S 4 ) with S i = 0 , 1, and adjacent nodes differ by one bit for 1 cycle: 576 patterns (sequence of 8 modes) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 10 / 34

  18. Context: Multilevel Converters Example : 5-level multilevel converter A priori, many switching sequences exist: paths of a graph where nodes correspond to modes ( S 1 S 2 S 3 S 4 ) with S i = 0 , 1, and adjacent nodes differ by one bit for 1 cycle: 576 patterns (sequence of 8 modes) for n cycles: (576) n paths G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 10 / 34

  19. Context: Multilevel Converters Capacitor Voltage Balance Requirement G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 11 / 34

  20. Context: Multilevel Converters Capacitor Voltage Balance Requirement Actually, a control path is admissible only if the capacitor voltages fluctuate minimally between two switchings: capacitor voltage balancing property G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 11 / 34

  21. Context: Multilevel Converters Capacitor Voltage Balance Requirement Actually, a control path is admissible only if the capacitor voltages fluctuate minimally between two switchings: capacitor voltage balancing property Difficult in practice: after a few cycles, most control paths make the capacitor voltages ց 0 or the switches reach a blocking voltage value ( � collapse of the system) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 11 / 34

  22. Context: Multilevel Converters Capacitor Voltage Balance Requirement Actually, a control path is admissible only if the capacitor voltages fluctuate minimally between two switchings: capacitor voltage balancing property Difficult in practice: after a few cycles, most control paths make the capacitor voltages ց 0 or the switches reach a blocking voltage value ( � collapse of the system) The control problem is to find at each sampling time the appropriate sequence of switching modes which maintains the capacitor voltage balancing G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 11 / 34

  23. Context: Multilevel Converters Capacitor Voltage Balance Requirement Actually, a control path is admissible only if the capacitor voltages fluctuate minimally between two switchings: capacitor voltage balancing property Difficult in practice: after a few cycles, most control paths make the capacitor voltages ց 0 or the switches reach a blocking voltage value ( � collapse of the system) The control problem is to find at each sampling time the appropriate sequence of switching modes which maintains the capacitor voltage balancing In industry, use of heuristic rules in order to find predefined sequences of patterns and apply them repeatedly (no formal guarantee of capacitor voltage balance property) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 11 / 34

  24. Context: Multilevel Converters Our Approach We see: G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 12 / 34

  25. Context: Multilevel Converters Our Approach We see: the multilevel converter as a sampled switching system G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 12 / 34

  26. Context: Multilevel Converters Our Approach We see: the multilevel converter as a sampled switching system the control as state-dependent (depending on the electrical state of the system) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 12 / 34

  27. Context: Multilevel Converters Our Approach We see: the multilevel converter as a sampled switching system the control as state-dependent (depending on the electrical state of the system) the capacitor voltage balancing as a safety property G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 12 / 34

  28. Context: Multilevel Converters Our Approach We see: the multilevel converter as a sampled switching system the control as state-dependent (depending on the electrical state of the system) the capacitor voltage balancing as a safety property The problem is to synthesize a safety controller for the switching system (correct-by-design controller) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 12 / 34

  29. Controllability of Switched Systems Controllability of Switched Systems G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 13 / 34

  30. Controllability of Switched Systems What is a Sampled Switched System Formally G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 14 / 34

  31. Controllability of Switched Systems What is a Sampled Switched System Formally A state variable x G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 14 / 34

  32. Controllability of Switched Systems What is a Sampled Switched System Formally A state variable x A set of p modes U = { 1 , 2 , · · · , p } G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 14 / 34

  33. Controllability of Switched Systems What is a Sampled Switched System Formally A state variable x A set of p modes U = { 1 , 2 , · · · , p } Each mode u ∈ U is associated to a dynamic ˙ x = A u ( x ) + b u for some matrix A u and vector b u G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 14 / 34

  34. Controllability of Switched Systems What is a Sampled Switched System Formally A state variable x A set of p modes U = { 1 , 2 , · · · , p } Each mode u ∈ U is associated to a dynamic ˙ x = A u ( x ) + b u for some matrix A u and vector b u Sampled switching modes at t = τ, 2 τ, · · · G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 14 / 34

  35. Controllability of Switched Systems What is a Sampled Switched System Formally A state variable x A set of p modes U = { 1 , 2 , · · · , p } Each mode u ∈ U is associated to a dynamic ˙ x = A u ( x ) + b u for some matrix A u and vector b u Sampled switching modes at t = τ, 2 τ, · · · If x ( τ, x, u ) denotes the “successor” point reached by the system at time τ under mode u from initial condition x , then Post u ( X ) = { x ′ | x ( τ, x, u ) = x ′ for some x ∈ X } G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 14 / 34

  36. Controllability of Switched Systems What is a Sampled Switched System Formally A state variable x A set of p modes U = { 1 , 2 , · · · , p } Each mode u ∈ U is associated to a dynamic ˙ x = A u ( x ) + b u for some matrix A u and vector b u Sampled switching modes at t = τ, 2 τ, · · · If x ( τ, x, u ) denotes the “successor” point reached by the system at time τ under mode u from initial condition x , then Post u ( X ) = { x ′ | x ( τ, x, u ) = x ′ for some x ∈ X } Pre u ( X ) = { x | x ( τ, x, u ) = x ′ for some x ′ ∈ X } G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 14 / 34

  37. Controllability of Switched Systems Multilevel Converter as a Switched system The mode corresponds to the position of the switching cells S = ( S 1 , S 2 , S 3 , S 4 ) with S i ∈ { 0 , 1 } G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 15 / 34

  38. Controllability of Switched Systems Multilevel Converter as a Switched system The mode corresponds to the position of the switching cells S = ( S 1 , S 2 , S 3 , S 4 ) with S i ∈ { 0 , 1 } x = [ v 1 , v 2 , v 3 , i ] ⊤ with v i voltage across C i and i current of circuit G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 15 / 34

  39. Controllability of Switched Systems Multilevel Converter as a Switched system The mode corresponds to the position of the switching cells S = ( S 1 , S 2 , S 3 , S 4 ) with S i ∈ { 0 , 1 } x = [ v 1 , v 2 , v 3 , i ] ⊤ with v i voltage across C i and i current of circuit duration of cycle T = 8 τ G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 15 / 34

  40. Controllability of Switched Systems Multilevel Converter as a Switched system The mode corresponds to the position of the switching cells S = ( S 1 , S 2 , S 3 , S 4 ) with S i ∈ { 0 , 1 } x = [ v 1 , v 2 , v 3 , i ] ⊤ with v i voltage across C i and i current of circuit duration of cycle T = 8 τ The 5-level converter can be seen as a switched system. Given a mode S , the associated dynamics is of the form ˙ x ( t ) = A S x ( t ) + b S with: 1  S 1 − S 2    − 0 0 0 R 1 C 1 C 1 1 S 2 − S 3 0 − 0 0     R 2 C 2 C 2 A S =  b S =     1 S 3 − S 4 0 0 0 −     R 3 C 3 C 3    (2 S 1 − 1) v input S 2 − S 1 S 3 − S 2 S 4 − S 3 − R Load L Load L Load L Load L Load L Load G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 15 / 34

  41. Controllability of Switched Systems Safety Control Problem At every τ , find the appropriate mode p (or pattern π ) according to the current value of x , in order to always stay in a predefined safety zone R , corresponding here to capacitor voltage balancing (small fluctuation of the capacitor voltages) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 16 / 34

  42. Controllability of Switched Systems Safety Control Problem At every τ , find the appropriate mode p (or pattern π ) according to the current value of x , in order to always stay in a predefined safety zone R , corresponding here to capacitor voltage balancing (small fluctuation of the capacitor voltages) For a 5-level converter with a waveform of amplitude of 200 V , centered around 0 V , the ideal capacitor voltages are: v ∗ 1 = 150 V, v ∗ 2 = 100 V, v ∗ 3 = 50 V G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 16 / 34

  43. Controllability of Switched Systems Safety Control Problem At every τ , find the appropriate mode p (or pattern π ) according to the current value of x , in order to always stay in a predefined safety zone R , corresponding here to capacitor voltage balancing (small fluctuation of the capacitor voltages) For a 5-level converter with a waveform of amplitude of 200 V , centered around 0 V , the ideal capacitor voltages are: v ∗ 1 = 150 V, v ∗ 2 = 100 V, v ∗ 3 = 50 V If a fluctuation of ± 5 V is admissible, the safety area is: R = [145 , 155] × [95 , 105] × [45 , 55] G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 16 / 34

  44. State Decomposition State Decomposition G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 17 / 34

  45. State Decomposition Classical Safety Control Synthesis (Ramadge-Wonham) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 18 / 34

  46. State Decomposition Classical Safety Control Synthesis (Ramadge-Wonham) Given a safety area R G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 18 / 34

  47. State Decomposition Classical Safety Control Synthesis (Ramadge-Wonham) Given a safety area R Problem: Find all the points of R that can be controlled to always stay within R (controllable subset) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 18 / 34

  48. State Decomposition Classical Safety Control Synthesis (Ramadge-Wonham) Given a safety area R Problem: Find all the points of R that can be controlled to always stay within R (controllable subset) Alternatively: Find the maximal invariant subset M of R (i.e., largest M ⊆ R such that Post ( M ) ⊆ M ) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 18 / 34

  49. State Decomposition Classical Safety Control Synthesis (Ramadge-Wonham) Given a safety area R Problem: Find all the points of R that can be controlled to always stay within R (controllable subset) Alternatively: Find the maximal invariant subset M of R (i.e., largest M ⊆ R such that Post ( M ) ⊆ M ) k ≥ 0 ( Pre k ( R ))) Backward procedure ( � G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 18 / 34

  50. State Decomposition Classical Safety Control Synthesis (Ramadge-Wonham) Given a safety area R Problem: Find all the points of R that can be controlled to always stay within R (controllable subset) Alternatively: Find the maximal invariant subset M of R (i.e., largest M ⊆ R such that Post ( M ) ⊆ M ) k ≥ 0 ( Pre k ( R ))) Backward procedure ( � Drawbacks: Not always computable for infinite state systems Numerical instability for contractive systems G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 18 / 34

  51. State Decomposition Classical Safety Control Synthesis (Ramadge-Wonham) Given a safety area R Problem: Find all the points of R that can be controlled to always stay within R (controllable subset) Alternatively: Find the maximal invariant subset M of R (i.e., largest M ⊆ R such that Post ( M ) ⊆ M ) Backward procedure ( � k ≥ 0 ( Pre k ( R ))) Drawbacks: Not always computable for infinite state systems Numerical instability for contractive systems G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 18 / 34

  52. State Decomposition Classical Safety Control Synthesis (Ramadge-Wonham) Given a safety area R Problem: Find all the points of R that can be controlled to always stay within R (controllable subset) Alternatively: Find the maximal invariant subset M of R (i.e., largest M ⊆ R such that Post ( M ) ⊆ M ) Backward procedure ( � k ≥ 0 ( Pre k ( R ))) Drawbacks: Not always computable for infinite state systems Numerical instability for contractive systems G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 18 / 34

  53. State Decomposition Classical Safety Control Synthesis (Ramadge-Wonham) Given a safety area R Problem: Find all the points of R that can be controlled to always stay within R (controllable subset) Alternatively: Find the maximal invariant subset M of R (i.e., largest M ⊆ R such that Post ( M ) ⊆ M ) Backward procedure ( � k ≥ 0 ( Pre k ( R ))) Drawbacks: Not always computable for infinite state systems Numerical instability for contractive systems G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 18 / 34

  54. State Decomposition Alternative: Reasoning with patterns instead of modes For uncontrollable points, find a pattern (sequence of modes) which makes the point go back to R G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 19 / 34

  55. State Decomposition Alternative: Reasoning with patterns instead of modes For uncontrollable points, find a pattern (sequence of modes) which makes the point go back to R Advantage: uniformity: the same pattern can be applied to a subregion of R (found by “decomposition”) decomposition in regions based on forward computation ( Post ) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 19 / 34

  56. State Decomposition Alternative: Reasoning with patterns instead of modes For uncontrollable points, find a pattern (sequence of modes) which makes the point go back to R Advantage: uniformity: the same pattern can be applied to a subregion of R (found by “decomposition”) decomposition in regions based on forward computation ( Post ) Drawbacks: Intermediate steps may exit from R (safety not ensured for R but for a superset R ∗ of R ) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 19 / 34

  57. State Decomposition Alternative: Reasoning with patterns instead of modes For uncontrollable points, find a pattern (sequence of modes) which makes the point go back to R Advantage: uniformity: the same pattern can be applied to a subregion of R (found by “decomposition”) decomposition in regions based on forward computation ( Post ) Drawbacks: Intermediate steps may exit from R (safety not ensured for R but for a superset R ∗ of R ) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 19 / 34

  58. State Decomposition Sketch of the Decomposition Method Given a zone R G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 20 / 34

  59. State Decomposition Sketch of the Decomposition Method Given a zone R Look for a pattern which maps R into R G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 20 / 34

  60. State Decomposition Sketch of the Decomposition Method Given a zone R Look for a pattern which maps R into R If such a pattern exists, then uniform control over the whole R G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 20 / 34

  61. State Decomposition Sketch of the Decomposition Method Given a zone R Look for a pattern which maps R into R If such a pattern exists, then uniform control over the whole R Otherwise, bisection of R , and search for patterns mapping subparts into R G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 20 / 34

  62. State Decomposition Sketch of the Decomposition Method Given a zone R Look for a pattern which maps R into R If such a pattern exists, then uniform control over the whole R Otherwise, bisection of R , and search for patterns mapping subparts into R In case of failure, iterate the bisection G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 20 / 34

  63. State Decomposition More Formally Given a set R , find by iterated bisection a decomposition ∆, i.e., a set of couples { ( V i , π i ) } i ∈ I such that: G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 21 / 34

  64. State Decomposition More Formally Given a set R , find by iterated bisection a decomposition ∆, i.e., a set of couples { ( V i , π i ) } i ∈ I such that: � i ∈ I V i = R G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 21 / 34

  65. State Decomposition More Formally Given a set R , find by iterated bisection a decomposition ∆, i.e., a set of couples { ( V i , π i ) } i ∈ I such that: � i ∈ I V i = R ∀ i ∈ I Post π i ( V i ) ⊆ R . G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 21 / 34

  66. State Decomposition More Formally Given a set R , find by iterated bisection a decomposition ∆, i.e., a set of couples { ( V i , π i ) } i ∈ I such that: � i ∈ I V i = R ∀ i ∈ I Post π i ( V i ) ⊆ R . G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 21 / 34

  67. State Decomposition Control Induced by the Decomposition The decomposition ∆ = { ( V i , π i ) } i ∈ I induces a control as follows: G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 22 / 34

  68. State Decomposition Control Induced by the Decomposition The decomposition ∆ = { ( V i , π i ) } i ∈ I induces a control as follows: 1 x ( t ) ∈ R , therefore ∃ i ∈ I such that x ( t ) ∈ V i G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 22 / 34

  69. State Decomposition Control Induced by the Decomposition The decomposition ∆ = { ( V i , π i ) } i ∈ I induces a control as follows: 1 x ( t ) ∈ R , therefore ∃ i ∈ I such that x ( t ) ∈ V i 2 Apply pattern π i to x ( t ) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 22 / 34

  70. State Decomposition Control Induced by the Decomposition The decomposition ∆ = { ( V i , π i ) } i ∈ I induces a control as follows: 1 x ( t ) ∈ R , therefore ∃ i ∈ I such that x ( t ) ∈ V i 2 Apply pattern π i to x ( t ) 3 At the end of π i , x ( t ′ ) ∈ R , iterate by going back to step (1) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 22 / 34

  71. State Decomposition Control Induced by the Decomposition The decomposition ∆ = { ( V i , π i ) } i ∈ I induces a control as follows: 1 x ( t ) ∈ R , therefore ∃ i ∈ I such that x ( t ) ∈ V i 2 Apply pattern π i to x ( t ) 3 At the end of π i , x ( t ′ ) ∈ R , iterate by going back to step (1) Property Under the induced control, the system always returns in R after each pattern application G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 22 / 34

  72. State Decomposition Control Induced by the Decomposition The decomposition ∆ = { ( V i , π i ) } i ∈ I induces a control as follows: 1 x ( t ) ∈ R , therefore ∃ i ∈ I such that x ( t ) ∈ V i 2 Apply pattern π i to x ( t ) 3 At the end of π i , x ( t ′ ) ∈ R , iterate by going back to step (1) Property Under the induced control, the system always returns in R after each pattern application NB: The basic procedure can be refined with an extended safety set R ∗ in order to guarantee that all the intermediate points are in R ∗ at each sampling time. G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 22 / 34

  73. State Decomposition Trajectory under the induced control G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 23 / 34

  74. Application to Multilevel Converters Application to Multilevel Converters G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 24 / 34

  75. Application to Multilevel Converters Case Study: a Multilevel Converter A prototype built by SATIE Lab for the Farman project BOOST2 The general function of a multilvel converter is to synthesize a desired AC voltage from several levels of DC voltages. G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 25 / 34

  76. Application to Multilevel Converters Application to Multilevel Converter (5 levels) Figure : Electric scheme and ideal output for 5-level converter Objective: Find appropriate switching strategy in order to obtain the desired staircase output voltage while keeping capacitor voltage balancing G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 26 / 34

  77. Application to Multilevel Converters Application of Decomposition Procedure v input = 100 V , R load = 50Ω, C 1 = C 2 = C 3 = 0 . 0012 F , L load = 0 . 2 H , R 1 = R 2 = R 3 = 20 , 000Ω, T = 8 τ = 0 . 02 s (frequency 50Hz) R = [145 , 155] × [95 , 105] × [45 , 55] procedure successful using only one bisection by dimension G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 27 / 34

  78. Application to Multilevel Converters Numerical Simulations of the Capacitor Voltages (a) v C 1 = f ( t ) (b) v C 2 = f ( t ) (c) v C 3 = f ( t ) (d) projection on (e) projection on (f) projection on ( v C 1 , v C 2 ) ( v C 1 , v C 3 ) v C 2 , v C 3 ) G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 28 / 34

  79. Application to Multilevel Converters Numerical Simulation of the Output Voltage G. Feld 2 , L. Fribourg 1 , D. Labrousse 2 , B. Revol 2 , R. Soulat 1 ( 1 LSV, 2 SATIE - ENS Cachan & CNRS) Correct-by-Design Control Synthesis for Multilevel Converters using State Space FSFMA, 13 May 2014 29 / 34

Recommend

CS137: Today Electronic Design Automation Multilevel Synthesis/Optimization Why

CS137: Today Electronic Design Automation Multilevel Synthesis/Optimization Why

CS137: Today Electronic Design Automation Multilevel Synthesis/Optimization Why Transforms -- defined Day 5: October 7, 2005 Division/extraction Multi-level Synthesis How we support transforms Boolean Division

358 views • 9 slides
Part III Part III Gain- -based synthesis based synthesis Gain enabler for correct- -by

Part III Part III Gain- -based synthesis based synthesis Gain enabler for correct- -by

Part III Part III Gain- -based synthesis based synthesis Gain enabler for correct- -by by- -construction design construction design enabler for correct ASP- -DAC01 Tutorial DAC01 Tutorial ASP Patrick Groeneveld

1k views • 87 slides
Non-zero sum games and control February 3, 2015,

Non-zero sum games and control February 3, 2015,

Correct-by-construc-on control synthesis for highly dynamics systems: an applica-on in automo-ve safety systems Necmiye Ozay EECS, University of Michigan

485 views • 29 slides
On the synthesis of provably correct discrete controllers Jri Vain Dept. of Computer

On the synthesis of provably correct discrete controllers Jri Vain Dept. of Computer

On the synthesis of provably correct discrete controllers Jri Vain Dept. of Computer Science/Institute of Cybernetics Tallinn University of Technology Eesti arvutiteaduse teooriapev, sgis 2004 1 Controller synthesis problem (I)

393 views • 25 slides
Multilevel TRILL draft-perlman-trill-rbridge-multilevel-00.txt Radia Perlman

Multilevel TRILL draft-perlman-trill-rbridge-multilevel-00.txt Radia Perlman

Multilevel TRILL draft-perlman-trill-rbridge-multilevel-00.txt Radia Perlman radiaperlman@gmail.com Intel Labs March 2011 1 Potential scalability issues routing computation load volatility of LSP database too much control traffic

828 views • 30 slides
Summary Summary I Iterative flow Iterative flow vs vs. stepwise refinement . stepwise

Summary Summary I Iterative flow Iterative flow vs vs. stepwise refinement . stepwise

Gain Gain-based synthesis based synthesis enabler for correct enabler for correct-by by-construction design construction design Patrick Patrick Groeneveld Groeneveld (patrick patrick@magma @magma-da da.com) .com) Magma

1.06k views • 46 slides
Outline Unix-style access control, contd CSci 5271 Multilevel and mandatory access control

Outline Unix-style access control, contd CSci 5271 Multilevel and mandatory access control

Outline Unix-style access control, contd CSci 5271 Multilevel and mandatory access control Introduction to Computer Security Access control, contd Announcements intermission Stephen McCamant Capability-based access control University

380 views • 7 slides
Digital'System'Design FSMD'Design:'complex'datapaths'+'complex' control'

Digital'System'Design FSMD'Design:'complex'datapaths'+'complex' control'

Digital'System'Design FSMD'Design:'complex'datapaths'+'complex' control' Controller'Design'Specified'as'ASM'Chart' Implemented'with'HDL So'far,'Datapath'Design'Accomplished'in'ad' hoc'Manner Use'Behavioral'Synthesis

412 views • 17 slides
Synthesis of Embedded Control Software Ufuk Topcu Caltech, Control and Dynamical Systems

Synthesis of Embedded Control Software Ufuk Topcu Caltech, Control and Dynamical Systems

Synthesis of Embedded Control Software Ufuk Topcu Caltech, Control and Dynamical Systems Papers, slides, notes, software tools at www.cds.caltech.edu/~UTopcu CMACS, CMU, Fall 2010 Synthesis of Embedded Control Software Joint work with N.

628 views • 52 slides
Outline Multilevel and mandatory access control CSci 5271 Capability-based access control

Outline Multilevel and mandatory access control CSci 5271 Capability-based access control

Outline Multilevel and mandatory access control CSci 5271 Capability-based access control Introduction to Computer Security Announcements intermission Day 11: OS security: higher assurance Stephen McCamant OS trust and assurance University

303 views • 9 slides
VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for

VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for

VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for synthesis General guidelines for hardware designers This lecture includes the content from: Nitin Yogi, Modelling for Synthesis with VHDL, Auburn

697 views • 52 slides
A multilevel stochastic gradient algorithm for PDE-constrained optimal control problems under

A multilevel stochastic gradient algorithm for PDE-constrained optimal control problems under

A multilevel stochastic gradient algorithm for PDE-constrained optimal control problems under uncertainty Fabio Nobile CSQI Institute of Mathematics, EPFL, Switzerland Joint work with : M. Martin (Criteo, Grenoble), S. Krumscheid (RWTH

841 views • 66 slides
Outline Multilevel and mandatory access control CSci 5271 Introduction to Computer Security

Outline Multilevel and mandatory access control CSci 5271 Introduction to Computer Security

Outline Multilevel and mandatory access control CSci 5271 Introduction to Computer Security Announcements intermission Day 10: OS security: access control Stephen McCamant Capability-based access control University of Minnesota, Computer

245 views • 5 slides
Outline Multilevel and mandatory access control CSci 5271 Introduction to Computer Security

Outline Multilevel and mandatory access control CSci 5271 Introduction to Computer Security

Outline Multilevel and mandatory access control CSci 5271 Introduction to Computer Security Announcements intermission Day 10: OS security: access control Stephen McCamant Capability-based access control University of Minnesota, Computer

486 views • 7 slides
Outline Database Security: Research Motivation and Practice Access Control Multilevel

Outline Database Security: Research Motivation and Practice Access Control Multilevel

Outline Database Security: Research Motivation and Practice Access Control Multilevel Relational Data Model Concurrency and Object Oriented Elisa Bertino, Sushil Jajodia and issues Pierangela Samarati Conclusions Presented

492 views • 5 slides
Basic Synthesis Flow and Commands Technology Libraries Design Read/Write Design

Basic Synthesis Flow and Commands Technology Libraries Design Read/Write Design

Introduction to Digital VLSI Logic Synthesis Basic Synthesis Flow and Commands Technology Libraries Design Read/Write Design Objects Timing Paths Constraints Compile Wire Load Models Multiple

851 views • 67 slides
Logic Synthesis Overview Design flow Principles of logic synthesis Logic

Logic Synthesis Overview Design flow Principles of logic synthesis Logic

Logic Synthesis Overview Design flow Principles of logic synthesis Logic Synthesis with the common tools Conclusions 2 System Design Flow Electronic System Level (ESL) flow System C TLM, Verification, Profiling

1.12k views • 28 slides
Why Again Logic Synthesis Giovanni De Micheli Why again logic synthesis? Strong

Why Again Logic Synthesis Giovanni De Micheli Why again logic synthesis? Strong

Why Again Logic Synthesis Giovanni De Micheli Why again logic synthesis? Strong intellectual value associated with logic synthesis and optimization Problems are far from being solved Current methods and tools grew out of control

372 views • 24 slides
Design, Synthesis and in vitro Screening of Pyrazolines based compounds as Phytohaemagglutinin (

Design, Synthesis and in vitro Screening of Pyrazolines based compounds as Phytohaemagglutinin (

Design, Synthesis and in vitro Screening of Pyrazolines based compounds as Phytohaemagglutinin ( PHA) mimetic Raj Kumar 1, *, Gaurav Joshi 1 , and Sandeep Singh 2 1 Laboratory for Drug Design and Synthesis, Centre for Pharmaceutical Sciences and

1.8k views • 21 slides
Lab 2 discussion Last Time Debugging Its a science use experiments to refine

Lab 2 discussion Last Time Debugging Its a science use experiments to refine

size= 64 correct= 0 size= 73 correct= 0 Shuying Liang size= 107 correct= 1 size= 107 correct= 0 size= 108 correct= 0 size= 108 correct= 1 Please do not handin a .doc file, a .zip file, a .tar file, size= 111 correct= 1 size=

430 views • 7 slides
Hardware Design with VHDL Synthesis of VHDL Code ECE 443 Synthesis of VHDL Code This slide set

Hardware Design with VHDL Synthesis of VHDL Code ECE 443 Synthesis of VHDL Code This slide set

Hardware Design with VHDL Synthesis of VHDL Code ECE 443 Synthesis of VHDL Code This slide set covers Fundamental limitation of EDA software Realization of VHDL operator Realization of VHDL data type VHDL synthesis flow

511 views • 34 slides
Open loop synthesis for closed loop control Kazufumi Ito, North Carolina State University June

Open loop synthesis for closed loop control Kazufumi Ito, North Carolina State University June

Open loop synthesis for closed loop control Kazufumi Ito, North Carolina State University June 22-26, 2015, FROM OPEN TO CLOSED LOOP CONTROL, Graz, Austria Closed loop synthesis Receding horizon synthesis Lagrange manifold method

426 views • 14 slides
Agenda 1. More on multilevel R formulas 2. Generalized Multilevel Models 3. GMLM in R 1 More

Agenda 1. More on multilevel R formulas 2. Generalized Multilevel Models 3. GMLM in R 1 More

Agenda 1. More on multilevel R formulas 2. Generalized Multilevel Models 3. GMLM in R 1 More on multilevel R formulas 2 Building a two-level model <latexit

620 views • 22 slides
Control and Synthesis, from a Distributed Perspective Anca Muscholl VTSA Summer School, Nancy,

Control and Synthesis, from a Distributed Perspective Anca Muscholl VTSA Summer School, Nancy,

Control and Synthesis, from a Distributed Perspective Anca Muscholl VTSA Summer School, Nancy, August 2018 1 / 104 Outline 1 Introduction 2 Basics on automata and logic 3 Basics on synthesis and control: Churchs problem 4 Distributed

1.96k views • 170 slides

More recommend