Computer Engineering Capstone Design Summer A 19982000: Handheld - PowerPoint PPT Presentation

Computer Engineering Capstone Design Summer A 1998–2000: Handheld Video Games J. S. McDonald IEEE/HKN Odd-Wednesday Talks May 24, 2000 http://www.kettering.edu/~mcdonald/ece403/

PIC-Pong • By Rickard Gun´ ee; uses a 4-MHz PIC16F84 and a TV(!) • the game in action: • the game: IEEE/HKN Slide 1

Original GameBoy Patent IEEE/HKN Slide 2

GameBoy Patent Drawings IEEE/HKN Slide 3

GameBoy Block Diagram IEEE/HKN Slide 4

GameBoy Schematic IEEE/HKN Slide 5

Project Overview (1999) In a Nutshell Design and build a hand-held video game. Some Details The game must • use a Microchip PIC 16C74A microcontroller • use a Micro Electronics SG128128 graphic LCD module • have an appropriate soundtrack and/or sound effects • be battery-powered, compact, and sturdily constructed • survive evaluation by a dozen 5th-graders!?!! IEEE/HKN Slide 6

Project History • 1998: “Original Edition Handheld Video Games”: – no sound, makeshift buttons and cases – Games: Street Fighter, Battleship, Breakout, PIC Pilot • 1999: “Handheld Video Games II”: – one- or two-track sound, real NES buttons, smaller cases – Games: Combat!, Bowling, Go Banana!, Tetris, Missile Command, Duel Tetris, PICman • 2000: “Ultimate Handheld Video Games” (as in, the last): – custom printed-circuit boards, even smaller cases, in-circuit emulator for development – Games: ??? IEEE/HKN Slide 7

✂ � ☎ ✄ ✁ � PIC Overview • Harvard architecture (separate instruction and data memories) – 14-bit instructions – 8-bit data • Single-cycle instruction execution via instruction pre-fetch Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 • 200-ns instruction cycle • Reduced instruction set (35 total) . . . IEEE/HKN Slide 8

PIC Instruction Set 14-Bit Instruction Word Status Mnemonic, Description Cycles Bits Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS 00 0111 dfff ffff ADDWF f, d Add W and f 1 C,DC,Z 1,2 00 0101 dfff ffff ANDWF f, d AND W with f 1 Z 1,2 00 0001 lfff ffff CLRF f Clear f 1 Z 2 00 0001 0xxx xxxx CLRW - Clear W 1 Z 00 1001 dfff ffff COMF f, d Complement f 1 Z 1,2 00 0011 dfff ffff DECF f, d Decrement f 1 Z 1,2 00 1011 dfff ffff DECFSZ f, d Decrement f, Skip if 0 1(2) 1,2,3 00 1010 dfff ffff INCF f, d Increment f 1 Z 1,2 00 1111 dfff ffff INCFSZ f, d Increment f, Skip if 0 1(2) 1,2,3 00 0100 dfff ffff IORWF f, d Inclusive OR W with f 1 Z 1,2 00 1000 dfff ffff MOVF f, d Move f 1 Z 1,2 00 0000 lfff ffff MOVWF f Move W to f 1 00 0000 0xx0 0000 NOP - No Operation 1 00 1101 dfff ffff RLF f, d Rotate Left f through Carry 1 C 1,2 00 1100 dfff ffff RRF f, d Rotate Right f through Carry 1 C 1,2 00 0010 dfff ffff SUBWF f, d Subtract W from f 1 C,DC,Z 1,2 00 1110 dfff ffff SWAPF f, d Swap nibbles in f 1 1,2 00 0110 dfff ffff XORWF f, d Exclusive OR W with f 1 Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS 01 00bb bfff ffff BCF f, b Bit Clear f 1 1,2 01 01bb bfff ffff BSF f, b Bit Set f 1 1,2 01 10bb bfff- ffff BTFSC f, b Bit Test f, Skip if Clear 1 (2) 3 01 11bb bfff ffff BTFSS f, b Bit Test f, Skip if Set 1 (2) 3 LITERAL AND CONTROL OPERATIONS 11 111x kkkk kkkk ADDLW k Add literal and W 1 C,DC,Z 11 1001 kkkk kkkk ANDLW k AND literal with W 1 Z 10 0kkk kkkk kkkk CALL k Call subroutine 2 00 0000 0110 0100 CLRWDT - Clear Watchdog Timer 1 TO , PD 10 1kkk kkkk kkkk GOTO k Go to address 2 11 1000 kkkk kkkk IORLW k Inclusive OR literal with W 1 Z 11 00xx kkkk kkkk MOVLW k Move literal to W 1 00 0000 0000 1001 RETFIE - Return from interrupt 2 11 01xx kkkk kkkk RETLW k Return with literal in W 2 00 0000 0000 1000 RETURN - Return from Subroutine 2 00 0000 0110 0011 SLEEP - Go into standby mode 1 TO , PD 11 110x kkkk kkkk SUBLW k Subtract W from literal 1 C,DC,Z 11 1010 kkkk kkkk XORLW k Exclusive OR literal with W 1 Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1 ), the value used will be that IEEE/HKN Slide 9

✞ ✡ ✄ ✆ ✝ ☎ ✂ ✆ ✁ ✆ ✝ ✝ ✟ ✠ ✡ ✡ ✄ � ✡ � � ✁ ☛ � � ☞ ✌ ✌ � ☞ ☎ PIC 16C74A 13 8 PORTA Data Bus Program Counter RA0/AN0 EPROM RA1/AN1 RA2/AN2 Program RAM RA3/AN3/V REF Memory 8 Le vel Stack RA4/T0CKI (13-bit) File RA5/SS/AN4 Registers Program 14 RAM Addr (1) Bus 9 PORTB Addr MUX Instruction reg RB0/INT Indirect 7 Direct Addr 8 Addr RB7:RB1 FSR reg STATUS reg PORTC 8 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 3 MUX Power-up RC3/SCK/SCL Timer RC4/SDI/SDA Oscillator RC5/SDO Instruction Decode & Start-up Timer RC6/TX/CK ALU Control RC7/RX/DT Power-on 8 PORTD Reset Timing W atchdog W reg Generation Timer OSC1/CLKIN Brown-out Reset (2) RD7/PSP7:RD0/PSP0 OSC2/CLK OUT PORTE Parallel Slave Port MCLR V , V SS DD RE0/RD/AN5 RE1/WR/AN6 Timer0 Timer1 Timer2 A/D RE2/CS/AN7 Synchronous USART CCP1 CCP2 Serial Port • 4K program and 192-byte data memories • 33 I/Os, including 8 A/D IEEE/HKN Slide 10

� ✆ ✆ ✆ ✆ ✆ ✆ ✆ ✆ ✆ ✆ ✆ ✆ ✆ ✆ ☎ � ✆ ☎ ✝ ✞ ✂ ✝ ✂ ✂ ✁ ✁ ✝ ✂ � ✟ ✟ ✁ ✝ ☎ ✆ ☎ ✄ ✄ ✄ ☎ ✄ ✄ ✄ ✄ ✄ ✄ � � ✂ ✁ � ✄ ✄ ✄ ✄ ☎ ☎ ☎ ☎ ☎ ☎ ☎ ☎ ✄ ☎ ☎ ☎ ✄ ✄ PIC 16C74A Registers File File Address Address INDF (1) INDF (1) 00h 80h 81h 01h TMR0 OPTION 02h PCL PCL 82h 03h STATUS STATUS 83h 04h FSR FSR 84h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 07h PORTC TRISC 87h PORTD (2) TRISD (2) 08h 88h PORTE (2) TRISE (2) 09h 89h 0Ah PCLATH PCLATH 8Ah 0Bh 8Bh INTCON INTCON 0Ch PIR1 PIE1 8Ch 0Dh PIR2 PIE2 8Dh 8Eh 0Eh TMR1L PCON 0Fh TMR1H 8Fh 10h T1CON 90h 11h TMR2 91h 12h T2CON PR2 92h 13h SSPB UF SSP ADD 93h 14h SSPCON SSPST AT 94h 15h 95h CCPR1L 16h CCPR1H 96h 17h CCP1CON 97h 98h 18h RCSTA TXSTA 19h TXREG SPBRG 99h 1Ah RCREG 9Ah 9Bh 1Bh CCPR2L 1Ch CCPR2H 9Ch 1Dh CCP2CON 9Dh 1Eh ADRES 9Eh 1Fh ADCON0 9Fh ADCON1 20h A0h Gener al Gener al Purpose Purpose Register Register FFh 7Fh Bank 0 Bank 1 IEEE/HKN Slide 11

Development Environment • PICDEM-2 demonstration board • MPLAB IDE (Integrated Development Environment) – assembler – linker – excellent simulator Free for download, with many useful application notes • Chipmaster 6000 device programmer • U-V eraser IEEE/HKN Slide 12

PICDEM-2 Demonstration Board +5V +5V +5V +5V +5V R6 C10 RA R5 Notes: C2 1 RA0 Unless otherwise specified, R1 R7 330 2 RA1 10K 0.1 4.7K 4.7K resistance values are in ohms, S1 S3 3 RA2 0.1 +5V J3 1 5% 1/4W. Capacitance values 4 RA3 8 RE U4 5 RA4 2 are in microfarads. C1 U1 1 VDD 6 RA5 RE0 3 A0 0.1 2 11 8 RE1 RA1 4 A1 R17 VDD RE0 C9 RA2 5 3 32 9 RE2 A2 470 VDD RE1 0.1 +5V NMCLR 1 10 RA3 6 24LC01B MCLR RE2 FOR 6 RA0 2 19 RD0 7 SCL 5 R2 RA0 RD0 LCD 7 SDA R16 RA1 3 20 RD1 8 WP RA1 RD1 DSPLY RA2 4 21 9 5K RD2 470 R18 RA2 RD2 VSS RA3 5 22 RD3 10 470 RA3 RD3 RA4 6 27 RD4 11 R19 RA4 RD4 +5V +5V RA5 7 28 RD5 12 470 RA5 RD5 C11 RB0 33 29 13 1 RD6 RB0 RD6 2 RB1 34 30 RD7 14 C12 RB1 RD7 0.1 3 RB2 35 15 OS0 0.1 R3 RB2 RC0 4 RB3 36 16 OS1 4.7K RB3 RC1 S2 5 RB4 37 17 RC2 U3 16 RB4 RC2 6 RB5 38 18 SCL RB5 RC3 VCC J1 7 RB6 39 23 SDA 2 V+ RB6 RC4 +5V 8 RB7 40 24 RC5 MAX232A 1 6 RB7 RC5 25 TX TX 11 14 2 T1IN T1OUT 7 RC6 RB 13 26 RX 10 7 3 T2IN T2OUT 8 R4 OSC1 RC7 4 4.7K RC 9 OSC2 12 14 RX 12 13 5 J7 VSS OSC2 1 (RC0) OSO R1OUT R1IN OSC1 31 9 8 VSS 2 (RC1) OSI R2OUT R2IN C3 3 RC2 PIC16C64 1 4 R14 4 (RC3) SCL C1+ C2+ 20PF 10 5 (RC4) SDA Provision Only 3 5 6 RC5 C1- C2- Y1 7 (RC6) TX C13 C15 6 8 (RC7) RX V- 0.1 0.1 C4 C5 GND TBD C14 KEYBOARD 20PF 20PF 15 RD 0.1 +5V J4 1 RD0 D1 RN3 Y2 RB0 R15 1 Not Populated 2 RD1 RB1 OUT 2 4 3 RD2 9 PIN HEADER 470 RB2 3 3 TXCO GRN 4 RD3 4 RB3 4 J2 POWER 5 RD4 +5V 1 5 C8 RN3 6 RD5 LM78L05 RB4 3 6 3 7 RD6 U5 2 C16 7 RN3 0.1 RB5 U2 8 RD7 1 IN OUT 4 0.01 8 DJ005A CR1 20 COM + + 9 RN3 VDD CR2 RB6 2 4 3 1N914 C17 C18 NMCLR 1 9 OSC1 Provision Only, +5V RN3 220 220 MCLR OSC1 J8 RB7 4 Not Populated C19 W02M R8 R9 0.1 RA0 2 10 OSC2 3 RN1 RA0 OSC2 Y3 RB0 +9V D2 RA1 3 10 10 RA1 Battery RA2 4 J5 RN1 RB1 RA2 D3 RA3 5 RA3 TBD +5V +5V +5V +5V RA4 6 Breadboard RN1 RB2 RA4 C6 C7 D4 RA5 7 20pF RA5 20pF RN1 R10 R11 R12 R13 RB3 D5 RB0 21 11 OSO 10 10 820 820 RB0 RC0 RN2 RB1 22 12 OSI RB4 D6 RB1 RC1 RB2 23 13 RC2 RB2 RC2 RN2 RB3 24 14 SCL RB5 D7 RB3 RC3 RB4 25 15 SDA RB4 RC4 RN2 RB6 RB5 26 16 RC5 D8 RB5 RC5 RB6 27 17 TX RN2 RB6 RC6 RB7 RB7 28 18 RX D9 RB7 RC7 8 VSS J6 19 VSS PIC16C73 X1 IEEE/HKN Slide 13