CISC Design: Implementation from HFC Virendra Singh Associate - PowerPoint PPT Presentation

CISC Design: Implementation from HFC Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in EE-739: Processor Design  Lecture 8 (29 Jan 2013)

Level 2 Flowcharts  Format for Level 2 flowchart state DR – Data Read  DW – Data Write Label B Label A  IR - Instruction Read Access Type  NA – No aceess ALU and CC • S – Set Tasks Duplicates • N – Not set • X – Don ’ t care Page and Loc Acess • BC – Branch conditionally State ID Synonym Next State Width • IB – Instruction branch • SB – Sequence branch • StateID – Direct branch  29 Jan 2013 EE-739@IITB 2

Level 2 Flowchart: Address Mode Sequences Base Plus Displacement (RY+d)@ ir edb  di na di  b  alu pc  a  alu, ao add-n add-n ry  a  alu +1  alu abdm1 abdm2 abdm3 abdm4 na dr edb  di t1  a  pc x-n x-n t1  b  ao, t2 abdm2 abdm3 abdm4 sb  29 Jan 2013 EE-739@IITB 3

Merged Level 2 Flowchart: Address Mode Sequences Base Plus Displacement (RY+d)@ ir edb  di na di  b  alu pc  a  alu, ao add-n add-n ry  a  alu +1  alu abdm1 abdm2 abdm3 abdm4 na dr edb  di t1  a  pc x-n x-n t1  b  ao, t2 abdm2 abdm3 abdm4 sb  29 Jan 2013 EE-739@IITB 4

Merged Level 2 Flowchart: Address Mode Sequences Register Indirect RY@ dr edb  di x-n ry  b  ao, t2 adrm1 sb  29 Jan 2013 EE-739@IITB 5

Merged Level 2 Flowchart: Address Mode Sequences Branch Instruction ir edb  irf ry  a  alu, ao add-n +1  alu brzz1 bc Z = 0 (no branch) Z = 1 (Branch) edb  irf ir pc  a  alu, ao add-n na +1  alu irf  ire x-n t1  b  pc brzz3 brzz2 brzz2 ib  29 Jan 2013 EE-739@IITB 6

Merged Level 2 Flowchart: Execution Sequences Execution sequences with memory operand reference Mem  RX LOAD Mem  RX STORE di  b  rx, t2 ir dw rx  a  alu, do edb  irf add-x t2  b  ao add-s pc  a  alu, ao 0  alu +1  alu strm1 brzz3 ldrm1 ldrm2 irf  ire na t1  b  pc add-s t2  a  alu 0  alu ldrm2 ib  29 Jan 2013 EE-739@IITB 7

Merged Level 2 Flowchart: Execution Sequences Execution sequences with memory operand reference RX OP Mem  Mem ADD, AND, SUB Mem  ALU TEST na di  b  alu di  b  t2 ir op-s rx  a  alu edb  irf add-x pc  a  alu, ao oprm1 oprm2 +1  alu dw test1 ldrm2 t1  a  do x-s t2  b  ao oprm2 brzz3  29 Jan 2013 EE-739@IITB 8

Merged Level 2 Flowchart: Execution Sequences Execution sequences for Register-to-Register and special instructions RX  RY LOAD RX OP RY  RY ADD, SUB, AND edb  irf ir na pc  a  alu, ao rx  a  alu add-x op-s ry  a  rx, t2 ry  b  alu +1  alu oprr1 oprr2 ldrr1 ldrm2 Edb  irf ir RX  RY STORE Pc  a  alu, ao Edb  irf add-n ir T1  a  ry Pc  a  alu, ao +1  alu add-x Rx  b  ry, t2 +1  alu oprr2 brzz2 strr1 ldrm2  29 Jan 2013 EE-739@IITB 9

Merged Level 2 Flowchart: Execution Sequences Execution sequences for Register-to-Register and special instructions RY-1  RY RY@  RX RY@  RX PUSH RY+1  RY POP na dr edb  di ry  a  alu add-n ry  a  alu, ao add-n -1  alu +1  alu push1 push2 popr1 popr2 dw na rx  a  do Di  b  rx x-n x-n t1  b  ao, ry T1  a  ry push2 brzz3 popr2 brzz3  29 Jan 2013 EE-739@IITB 10

Processor Block Diagram IB Next SB Control Instruction State B Store Decoder Control C D B Control Branch Word Register Control OP TY NA Control Fields (dynamic) Control word Control Fields IRE (Static) Decoders Condition IRF Control lines Codes Datapath  29 Jan 2013 EE-739@IITB 11

MIN Datapath IRE IRF Internal A Bus DO AO PC T2 R0 R1 Rn T1 ALU k DI Internal B Bus External Data External Address Bus (EDB) Bus (EAB)  29 Jan 2013 EE-739@IITB 12

Implementation  Each state in Level 2 flowchart corresponds to one control word  Transformation of flowcharts into control store bit patterns  The task become bits in the control fields (OP)  The next state becomes in the control store address select (TY) and next address (NA)  The state ID becomes the location of the control word in the control store  29 Jan 2013 EE-739@IITB 13

Implementation Relationship between Flowcharts and Hardware  Flowchart – compact and precise description of hardware requirements  Stepts for implementing microcoded controller 1. Execution Unit  Develop concurrently  Add things as and when needed  29 Jan 2013 EE-739@IITB 14

Implementation 2. Instruction Decoders  Translate an instruction bit pattern to the control store address for the execution sequence  Two decoders are needed (for MIN)  First, translates the instruction bit pattern into the control store address for the appropriate address mode sequence (provide IB)  Second, translates the instruction bit pattern into control store address for the execution sequence (provide SB)  29 Jan 2013 EE-739@IITB 15

Implementation 3. Control word format  Derived from flowcharts  HFC can tell required capability of control word precisely 4. Control word decoders  Combine control word (dynamic) control fields, the IRE (static) control fields, and timing signals, to provide the gate control signals for all transfers in the Datapath and the Controller 5. Controller block diagram  29 Jan 2013 EE-739@IITB 16

Implementation  Design of flowchart  Made some assumptions (buses, registers..)  Collect the assumptions and implement  29 Jan 2013 EE-739@IITB 17

MIN Datapath IRE IRF Internal A Bus DO AO PC T2 R0 R1 Rn T1 ALU k DI Internal B Bus External Data External Address Bus (EDB) Bus (EAB)  29 Jan 2013 EE-739@IITB 18

Instruction Decoders  Two decoders  First Decoder (IB decoder)  Points to the first control word in an address mode sequence (if there is one)  The last state in any execution sequence is IB  Second Decoder (SB decoder)  Points to the first control word of the execution sequence  The last sequence in addr. mode seq. is SB  29 Jan 2013 EE-739@IITB 19

Instruction Execution Sequences Instruction Control Word Next control IB SB Sequence word Instruction Instruction address Decoder Decoder POP popr1 popr2 --- --- popr2 brzz3 --- --- brzz3 brzz2 --- --- brzz2 --- abdm1 oprm1 ADD abdm1 abdm2 --- oprm1 RX(RY+d)@ abdm2 abdm3 --- oprm1 abdm3 abdm4 --- oprm1 abdm4 --- --- oprm1 oprm1 oprm2 --- --- oprm2 brzz3 --- --- brzz3 brzz2 --- --- brzz2 --- oprr1 ---  29 Jan 2013 20 EE-739@IITB

Instruction Execution Sequences Instruction Control Word Next control IB SB Sequence word Instruction Instruction address Decoder Decoder SUB RX RY oprr1 oprr2 --- --- oprr2 brzz2 --- --- brzz2 --- adrm1 test1 TEST RY@ adrm1 --- adrm1 test1 test1 ldrm2 --- --- ldrm2 --- push1 --- PUSH  29 Jan 2013 21 EE-739@IITB

IB Instruction Decoder IB Decoder Instruction(s) or Address Address Mode abdm1 (RY+d)@ Address mode sequences adrm1 RY@ brzz1 BZ Execution sequences ldrr1 LR (Instructions strr1 STR without separate oprr1 AR, SR, NR address mode sequences) popr1 POP push1 PUSH  29 Jan 2013 22 EE-739@IITB

SB Instruction Decoder SB Decoder Instruction(s) or Address Address Mode ldrm1 L Execution sequences (Instructions with strm1 ST separate address oprm1 A, S, N mode sequences) test1 T  29 Jan 2013 23 EE-739@IITB

Control Word Format  Control words  Operation section (OP) is composed of the fields for Datapath control  Next state section, containing TY and NA, contains the field for state sequencer control  If two macro in the Datapath are never used at the same time, you might consider sharing the control field OP TY NA  29 Jan 2013 EE-739@IITB 24

MIN Control Word Control Fields AO PC T2 Regs T1 ALU K DI DO IRE IRF …. MIN Execution Unit IRE IRF Internal A Bus DO AO PC T2 R0 R1 Rn T1 ALU k DI Internal B Bus (EDB) (EAB)  29 Jan 2013 EE-739@IITB 25

Control Word Decoder  How many bits each control needs?  Procedure 1. List uses of the macro 2. Allocate bits 3. Use a Karnaugh map to assign bit patterns  Collect all the occurrences (PC, T2, RX …)  Assign no. of bits to control fields  29 Jan 2013 EE-739@IITB 26

Control Word Decoder  PC Control  PC occurrences pc  a • a  pc (only one occurrence – abdm2) • b  pc • • none  29 Jan 2013 EE-739@IITB 27

PC Control Internal A Bus pca 0 1 pca 0 Pc  a none pcb PC b  pc x 1 pcb Internal B Bus  29 Jan 2013 28 EE-739@IITB