RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan Brent Nelson and Brad Hutchings FPL September 5-7, 2011
Why Build Your Own Tools Anyway? • Proof of concept in their own right – Hypothetical architectures may not account for all real-world factors • Targeting real chips important • The field needs wild and crazy ideas – The vendors don’t have all the answers! • That requires custom CAD tools 2
The Challenge • Building custom physical CAD Tools for commercial FPGAs == difficult – Closed, proprietary device databases – Unsupported interfaces • Architectural nuances complicate things… 3
Motivation #1: Rapid Prototyping quality of result (QOR) hours minutes seconds tool runtime
Motivation #1: Rapid Prototyping quality of result (QOR) Commercial tools focus here… hours minutes seconds tool runtime
Motivation #1: Rapid Prototyping For rapid prototyping and implementation we would like tools which focus here… quality of result (QOR) Commercial tools focus here… hours minutes seconds tool runtime
Motivation #2: Reliability • SEU mitigation using TMR – Selective duplication tools – Single-bit TMR failures in routing • Half-latch detection – Weak keeper tie-offs susceptible to SEUs • Need a way to do post-PAR analysis • Need a way to do post-PAR modifications 7
XDL: A Physical Database for Xilinx • A textual design database representation – For Xilinx designs • Available for many years Xilinx Xilinx Xilinx Xilinx .NCD .NCD .NCD .BIT par – r par – p bitgen map (place only) (route only) Xilinx Xilinx Xilinx xdl xdl xdl .XDL .XDL .XDL BYU Custom CAD Tools RapidSmith Tools 8
#1: XDL as a Design Representation Xilinx Xilinx Xilinx Xilinx .NCD .NCD .NCD .BIT par – r par – p bitgen map (place only) (route only) • xdl – ncd2xdl design Xilinx Xilinx Xilinx xdl xdl xdl – Converts NCD to XDL .XDL .XDL .XDL • xdl – xdl2ncd design BYU Custom CAD Tools RapidSmith Tools – Converts XDL back to NCD • Can inject own CAD tools at any point in the flow or bypass it entirely • Must convert back to NCD for bitgen 9
#2: XDLRC as a Device Description • xdl -report -pips -all_conns partName – Dumps textual description of specific device as a .xdlrc file – Details everything you need to write placers and routers (except timing data) 10
Challenges of XDLRC Device Descriptions • They are massive! – Up to 73GB of text for one device! – Difficult for tools to directly operate on XDLRC • They are missing some information – Primitive sites that support more than 1 type – Pin name mappings missing for some sites – Result: placement/routing inefficiencies occur • RapidSmith solves these problems 11
SOME TERMINOLOGY 12
A Familiar View of the Fabric… 13
A Familiar View of the Fabric… 14
A Familiar View of the Fabric… L_TERM INT_SO IOIS INT CLB INT CLB INT INT L_TERM INT_SO INT INT IOIS CLB CLB INT INT L_TERM INT_SO IOIS INT CLB INT CLB INT INT 15
XDLRC Abstraction – 2D Tile Array 16
XDLRC Abstraction - Tiles HCLK_X1Y39 INT_X2Y37 CLB_X2Y37 DSP_X10Y32 BRAM_X5Y32 17
XDLRC Abstraction – Primitive Sites INT_X2Y37 Contains: TIEOFF_X2Y37 CLB_X2Y37 Contains: DSP_X10Y32 SLICE_X3Y75 Contains: SLICE_X3Y74 DSP48_X0Y17 SLICE_X2Y75 DSP48_X0Y16 SLICE_X2Y74 BRAM_X5Y32 Contains: RAMB16_X0Y8 FIFO16_X0Y8 18
XDL EXAMPLES 19
XDL Example inst "inst23" "SLICEL", placed CLB_X13Y45 SLICE_X18Y91 , cfg " BXINV::BX BYINV::#OFF ... F:inst23lut0:#LUT:D=((~A1*A3)+(A1*A2)) G:inst23lut1:#LUT:D=((~A1*A3)+(A1*A4)) ... YUSED::#OFF "; ... net "shiftResult4" , cfg " ", inpin "inst4" G3 , outpin "inst5" YQ , ; 20
XDL Example inst "inst23" "SLICEL", placed CLB_X13Y45 SLICE_X18Y91 , cfg " BXINV::BX BYINV::#OFF ... F:inst23lut0:#LUT:D=((~A1*A3)+(A1*A2)) G:inst23lut1:#LUT:D=((~A1*A3)+(A1*A4)) ... YUSED::#OFF "; ... net "shiftResult4" , cfg " ", inpin "inst4" G3 , outpin "inst5" YQ , pip CLB_X31Y53 IMUX_B18_INT -> G3_PINWIRE2 , pip CLB_X31Y54 YQ_PINWIRE2 -> SECONDARY_LOGIC_OUTS6_INT , pip INT_X31Y53 OMUX_S3 -> IMUX_B18 , pip INT_X31Y54 SECONDARY_LOGIC_OUTS6 -> OMUX3 , ; 21
XDL Module Example module "mux" "inst23" , cfg " _SYSTEM_MACRO::FALSE "; port "mux5i_0_inport" "inst31" "F4"; port "mux5i_1_inport" "inst33" "F2"; ... inst "inst23" "SLICEL", placed CLB_X13Y45 SLICE_X18Y91 , cfg " BXINV::BX BYINV::#OFF ... YUSED::#OFF "; ... net "shiftResult4" , cfg " ", inpin "inst4" G3 , outpin "inst5" YQ , pip CLB_X31Y53 IMUX_B18_INT -> G3_PINWIRE2 , pip CLB_X31Y54 YQ_PINWIRE2 -> SECONDARY_LOGIC_OUTS6_INT , pip INT_X31Y53 OMUX_S3 -> IMUX_B18 , pip INT_X31Y54 SECONDARY_LOGIC_OUTS6 -> OMUX3 , ; endmodule "mux" ; 22
THE RAPIDSMITH TOOL SUITE 23
RapidSmith XDL File RapidSmith XDL File 24
RapidSmith XDL File RapidSmith Java Internal Graph API Represenation XDL File 25
RapidSmith XDL File RapidSmith Custom Cad Tools Java Internal Graph API ( create, place, Represenation route, modify circuits ) XDL File 26
RapidSmith Abstractions Design Device Tile Instance Net Module ModuleInstance (2D Array) Instance PrimitiveSite PrimitiveType NetType Port (List) TileType Wire (List) (Array) Attribute Pin Instance Net (List PrimitiveType (List) (List) (List) PIP PrimitiveSite Net (List) Tile (List) XDLRC XDL 28
XDLRC Device File Creation • Three major strategies to reduce XDLRC information size: – Aggressive wire and object reuse – Careful pruning of unnecessary wires – Customized serialization and compression • XDLRC size compression of >10,000X • Device files load in just a few seconds or less 29
RapidSmith Device Files Performance Xilinx Part XDLRC RapidSmith Memory Load Time Name Report Size File Size Footprint From Disk Virtex 4 LX200 10.0 GB 1.01 MB 61 MB 602 ms Virtex 5 LX330 12.5 GB 1.07 MB 69 MB 622 ms Virtex 6 CX240T 8.5 GB 0.94 MB 35 MB 460 ms Virtex 6 LX760 22.8 GB 1.76 MB 77 MB 1.07 s Virtex 7 855T 32.0 GB 2.63 MB 115 MB 1.41 s Virtex 7 2000T 73.6 GB 5.96 MB 301 MB 3.34 s 30
7 EXAMPLES OF RAPIDSMITH USE AND CAPABILITIES 31
RapidSmith Example #1: Random Placer public class RandomPlacer{ public static void main(String[] args){ // Create and load a design Design design = new Design(args[0]); Random rng = new Random(0); // Create random number generator // Place all unplaced instances for (Instance i : design.getInstances()){ if (i.isPlaced()) continue ; PrimitiveSite[] sites = design.getDevice().getAllCompatibleSites(i.getType()); int idx = rng.nextInt(sites.length); int watchDog = 0; // Find a free primitive site while (design.isPrimitiveSiteUsed(sites[idx])){ if (++idx > sites.length) idx = 0; if (++watchDog > sites.length) System.out.println("Placement failed."); } i.place(sites[idx]); } // Save the placed design design.saveXDLFile(args[1]); } 32 }
RapidSmith Example #2: Placing a Module // Load XDL file (parses XDL, populated design object) Design design = new Design("moduleContainingDesign.xdl"); // Get the 1024-FFT module definition by name Module fft = design.getModule("fft1024"); // Create an instance of the FFT module called "f0" ModuleInstance mi = design.createModuleInstance("f0", fft); //Find all compatible sites with the anchor PrimitiveType type = mi.getAnchor().getType(); PrimitiveSite[] sites = design.getDevice().getAllCompatibleSites(type); int i = 0; while (!mi.place(sites[i++], design.getDevice())){ if (i >= sites.length) error(mi.getName()+ " has no valid placement!"); } 33
RapidSmith Example #3: VCC/GND Handling • GND/VCC supplied in two ways: – LUTs configured to drive ‘1’ or ‘0’ – TIEOFF primitives in every switch box • Supplied GND / VCC posts • Router must partition nets into neighborhoods to use local static sources – RapidSmith includes a StaticSourceHandler class with a variety of methods to provide this functionality 34
RapidSmith Example #4: HMFlow • Rapid compilation approach using hard macros • Built on top of RapidSmith Design XDL Hard Design XDL .xdl .mdl Parser & Macro Stitcher Router Mapper Placer P LACED & I NPUT D ESIGNS R OUTED XDL Part of CHREC research project Generic HM HMG Demonstrated > 50X reduction in tool flow time Cache H ARD M ACRO S OURCES 35
RapidSmith Example #5: Device Browser 36
RapidSmith Example #6: Design Explorer 37
RapidSmith Example #7: Custom Hard Macro Placer 38
RapidSmith Example #7: Timing Visualizer
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