Chapter 5 Structural Specification of Hardware Part2 1 benyamin@mehr.sharif.edu
4-Bit Comparator Design b3 a3 b0 a0 b2 a2 b1 a1 A A A A A>B A>B A>B A>B B B B B A=B A=B A=B A=B > > > > = = = = A<B A<B A<B A<B < < < < 2 benyamin@mehr.sharif.edu
4-Bit Comparator Entity Declaration Entity nibble_comparator IS PORT( a,b:IN BIT_VECTOR(3 downto 0); gt,eq,lt: IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT ); END; 3 benyamin@mehr.sharif.edu
4-Bit Comparator Architecture Declaration Architecture iterative1 OF nibble_comparator IS SIGNAL im:BIT_VECTOR(0 TO 8); BEGIN c0:ENTITY WORK.bit_comparator PORT MAP (a(3),b(3),gt,eq,lt,im(0),im(1),im(2)); c1TOc2:FOR i in 1 to 2 GENERATE c:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; c3:ENTITY WORK.bit_comparator PORT MAP (a(0),b(0),im(6),im(7),im(8),a_gt_b,a_eq_b,a_lt_b); END; 4 benyamin@mehr.sharif.edu
Association List of Generate Statement PORT MAP ( a(i) , b(i) ,im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2) ); i=1 a(1) b(1) im(0) im(1) im(2) im(3) im(4) im(5) i=2 a(2) b(2) im(3) im(4) im(5) im(6) im(7) im(8) 5 benyamin@mehr.sharif.edu
Generate Statement Syntax Detail generate_lable : FOR generation_scheme GENERATE concurrent_statements END GENERATE; c1TOc2: generation lable FOR i IN 1 TO 2 GENERATE Generation scheme id IN x TO y c:ENTITY WORK.bit_comparator PORT MAP Id IN y DOWNTO x ((a(i),b(i),im(3*i-3),im(3*i-2),im(3*i- 1),im(3*i+0),im(3*i+1),im(3*i+2)); concurrent statement END GENERATE; 6 benyamin@mehr.sharif.edu
More on Iterative Hardware Architecture iterative2 OF nibble_comparator IS CONSTANT n : INTEGER:=4; SIGNAL im:BIT_VECTOR(0 TO 3*(n-1)-1 ); BEGIN Constant call:FOR i in n-1 downto 0 GENERATE Declaration IF i=n-1 GENERATE most:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i),gt,eq,lt,im(0),im(1),im(2)); END GENERATE; IF i>0 AND i<n-1 GENERATE rest:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; IF i=0 GENERATE least:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i), im(3*(n-1)-3),im(3*(n-1)-2),im(3*(n-1)-1),a_gt_b,a_eq_b,a_lt_b); END GENERATE; END GENERATE; END; 7 benyamin@mehr.sharif.edu
IF Generate Syntax Detail IF condition GENERATE concurrent statements END GENERATE IF i=n-1 GENERATE most:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i),gt,eq,lt,im(0),im(1),im(2)); END GENERATE; 8 benyamin@mehr.sharif.edu
More On Iterative Hardware Entity reg8 IS PORT(di:IN BIT_VECTOR(7 downto0); clk:IN BIT;qo:OUT BIT_VECTOR(7 downto 0)); END; ‘RANGE is an attribute for signals ARCHITECTURE iterative OF reg8 IS BEGIN that returns g: FOR I in di’RANGE GENERATE 7 downto 0 g07:ENTITY WORK.latch PORT MAP(di(i),clk,qo(i)); END GENERATE; END; 9 benyamin@mehr.sharif.edu
Modeling a Test Bench 1. Provides stimuli to the input ports of the entity 2. Test bench must contain the circuit under test 10 benyamin@mehr.sharif.edu
nibble_comparator Test Bench ENTITY Test IS END; ARCHITECTURE test OF test IS SIGNAL a,b,gtr,less,eql:BIT; SIGNAL gnd:BIT:=‘0’; SIGNAL vdd:BIT:=‘1’; BEGIN comp:ENTITY WORK.nibble_comparator(iterative2) PORT MAP (a,b,gnd,vdd,’0’,gtr,eql,lss); a<=“0000”,”1111” AFTER 50 ns, “1110” AFTER 150 ns; b<=“0000”,”1110” AFTER 150 ns, “1111” AFTER 250 ns; END; 11 benyamin@mehr.sharif.edu
OPEN Keyword •outputs of a component could be OPEN A A>B OPEN B A=B > = A<B < comp:ENTITY WORK.nibble_comparator(iterative2) PORT MAP (a,b,gnd,vdd,’0’, OPEN ,eql,lss); 12 benyamin@mehr.sharif.edu
OUT vs. BUFFER Entity ex IS PORT( a: IN BIT; m: IN BIT; b: OUT BIT; c: BUFFER BIT; OUT ); END; ARCHITECTURE sample OF ex IS BEGIN c<=m AND a; b<= NOT a WHEN c=‘1’ ; BUFFER END; 13 benyamin@mehr.sharif.edu
Formal Specification Details FOR lables : compe_name USE ENTITY Library.EntityName(ArchName) PORT MAP (association_list); Component COMPONENT n2 IS PORT(m,n:IN BIT;s:OUT BIT); END COMPONENT; FOR ALL:n2 USE Entity WORK.nand2(single) PORT MAP (x,y,z); C0: n2 port map (a,b,z); 14 benyamin@mehr.sharif.edu
Formal Specification Details Formal ports i1 i2 o1 Local ports x y z Component m n s ports Actual signals a b c 15 benyamin@mehr.sharif.edu
Chapter 6 Design Organization and Parameterization 16 benyamin@mehr.sharif.edu
Design Organization and Parameterization • Subprograms • Parameterizing and customizing design • Definition and usage of library packages • Generic design • Design configuration 17 benyamin@mehr.sharif.edu
Definition and Usage of Subprograms • Simplify coding • Modularity • Readability • Functions – Cannot alter the values of their parameters – Return a value • Procedures – Used as a statement – Can alter the values of its parameters 18 benyamin@mehr.sharif.edu
Function Declaration FUNCTION func_name (formal_parameter_list) RETURN return_type IS function_declarative_part variable and constant declaration BEGIN sequential statements –including RETURN statement; END func_name; • Subprograms can be declared in architecture declarative part or packages • Each function must have return expression • All formal parameters are considered IN mode 19 benyamin@mehr.sharif.edu
Functional Single-Bit Comparator Architecture functional OF bit_comparator IS FUNCTION fgl(w,x,gl:BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq(w,x,eq:BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; BEGIN a_gt_b<= fgl(a,b,gt) AFTER 12 NS; a_eq_b<= feq(a,b,eq) AFTER 12 NS; a_lt_b <= fgl(b,a,lt) AFTER 12 NS; END; 20 benyamin@mehr.sharif.edu
Concurrent Statements � Signal assignment � Component instantiation • Process statement � Concurrent procedure call • Block statement � Generate statement • Assertion statement 21 benyamin@mehr.sharif.edu
Sequential Statements � Signal assignment statement � Variable assignment statement • Wait statement � If,case,loop statement • Procedure call statement • Exit,return statement • Assertion statement 22 benyamin@mehr.sharif.edu
Variable Declaration VARIABLE identifier_list : type [ := init_value] ; Examples: VARIABLE a :BIT ; VARIABLE x : BIT := ‘1’; VARIABLE x,y,z : BIT_VECTOR(1 to 4) := “1011” ; VARIABLE b,i :INTEGER := -10; VARIABLE flag : BOOLEAN := TRUE; 23 benyamin@mehr.sharif.edu
Variable Assignment Target_variable := expression A := b AND c; A := c; X := (b and c) XOR b; i := i+1; Z := a*b+c/2-(w*t); 24 benyamin@mehr.sharif.edu
Control Statements � If-else statement • Case statement � For-loop statement � While-loop statement • Exit statement • Next statement 25 benyamin@mehr.sharif.edu
IF Statement IF condition THEN sequential statements; END IF; IF condition THEN IF condition THEN statements; statements; ELSIF condition THEN statements; ELSE ELSIF condition THEN statements; statements; ELSE statements; END IF; END IF; 26 benyamin@mehr.sharif.edu
IF Statement Example IF sel=‘1’ THEN IF sel=‘1’ THEN z<=i1; z<=i1; ELSIF sel=‘0’ THEN ELSE z<=i2; z<=i2; ELSE END IF; w<=‘0’ END IF; 27 benyamin@mehr.sharif.edu
FOR LOOP Statement FOR loop_counter IN Range LOOP sequential statements; END LOOP; Range ::= x TO y x<y | y DOWNTO x x<y | id’RANGE id is signal 28 benyamin@mehr.sharif.edu
FOR LOOP Example SIGNAL a:BIT_VECTOR(10 downto 0); SIGNAL b:BIT_VECTOR(0 to 10); …. b’RANGE FOR k IN 0 to 10 LOOP a(k)<=b(10-k); END LOOP; 29 benyamin@mehr.sharif.edu
WHILE LOOP Statement WHILE condition LOOP sequential statements; END LOOP; •Loop will continue until condition becomes FALSE 30 benyamin@mehr.sharif.edu
WHILE LOOP Example WHILE Enable=‘1’ LOOP Enable z<=‘1’; WAIT for 10 ns; PULSE Generator z<=‘0’; z WAIT for 10 ns; END LOOP; 20 ns 31 benyamin@mehr.sharif.edu
Procedure Call Declaration PROCEDURE proc_name (formal_parameter_list) IS procedure_declarative_part BEGIN sequential statements END proc_name; • Default class for inputs of subprograms are CONSTANT • Default class for outputs of subprograms are VARIABLE • In procedure declaration all input and outputs must be declared explicitly 32 benyamin@mehr.sharif.edu
Procedure Call Example PROCEDURE bin2int(bin:IN BIT_VECTOR(7 downto 0); int:OUT INTEGER) IS VARIABLE result:INTEGER; BEGIN result:=0; FOR i IN bin’RANGE LOOP IF bin(i)=‘1’ THEN result:=result+2**I; END IF; END FOR; END bin2int; 33 benyamin@mehr.sharif.edu
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