Chapter 4 Memory Process Control Flaxer Eli - Process Control Ch - PDF document

Chapter 4 Memory Process Control Flaxer Eli - Process Control Ch 4 - 1 Outline ● Read-Only Memory (ROM) – Internal Structure – Control and Timing ● Static RAM (SRAM) – Internal Structure – Control and Timing ● Dynamic RAM (DRAM) – Internal Structure – Control and Timing Flaxer Eli - Process Control Ch 4 - 2

Read-Only Memory (ROM) ● A combinational circuit with n inputs and b outputs: Address n b Data 2 n x b inputs outputs ROM A(n-1, ... , 0) D(b-1, ... , 0) ● Programmable  values determined by user ● Nonvolatile  contents retained without power Flaxer Eli - Process Control Ch 4 - 3 JZ Types Of ROMs (1) ● Mask ROM Bit Line – Connections made by the semiconductor vendor – Expensive setup cost Word Line – Several weeks for delivery – High volume only – Bipolar or MOS technology ● PROM – Programmable ROM – Connections made by equipment manufacturer – Vaporize (blow) fusible links with PROM programmer using high voltage/current pulses – Bipolar technology – One-time programmable Flaxer Eli - Process Control Ch 4 - 4 CLT

Types of ROMs (2) ● EPROM – Erasable Programmable ROM – Charge trapped on extra “floating gate” of MOS Bit Line transistors Word Line – Exposure to UV light removes charge ● 10-20 minutes ● Quartz Lid = expensive package – Limited number of erasures (10-100) ● EEPROM (E 2 ROM) – Electrically Erasable ROM – Floating gates charged/discharged electrically – Not RAM! (relatively slow charge/discharge) – limited number of charge/discharge cycles (10,000) Flaxer Eli - Process Control Ch 4 - 5 CLT Types of ROMs (3) ● Flash Memory – Electronically erasable in blocks – 100,000 erase cycles – Simpler and denser than EEPROM Flaxer Eli - Process Control Ch 4 - 6 CLT

Outline ● Read-Only Memory (ROM) – Internal Structure – Control and Timing ● Static RAM (SRAM) – Internal Structure – Control and Timing ● Dynamic RAM (DRAM) – Internal Structure – Control and Timing Flaxer Eli - Process Control Ch 4 - 7 Basic Structure of SRAM Bi Directional Bus 2 n x b RAM 2 n x b RAM A 0 A 0 A 1 A 1 A n-1 A n-1 DIN 0 DOUT 0 D 0 DIN 1 DOUT 1 D 1 DIN b-1 DOUT b-1 D b-1 CS CS OE OE WE WE ● Address/Control/Data Out lines like a ROM (Reading) + Write Enable (WE) and Data In (DIN) (Writing) Flaxer Eli - Process Control Ch 4 - 8 JAL

One Bit of SRAM IN D Q OUT IN OUT SEL /SEL WR C /WR ● SEL and WR asserted → IN data stored in D-latch (Write) ● SEL only asserted → D-latch output enabled (Read) ● SEL not asserted → No operation Flaxer Eli - Process Control Ch 4 - 9 JAL READ Timing (SRAM) Like a ROM! max(t AA, t ACS ) ADDR stable stable stable ≥ t AA /CS t OH t ACS /OE t OZ t OE t AA t OZ t OE DOUT valid valid valid Primary Spec for SRAMs Flaxer Eli - Process Control Ch 4 - 10 JAL

WRITE Timing (SRAM) (WE-controlled write) (CS-controlled write) ADDR stable stable t CSW t AS t CSW /CS t WP t AH t AS t WP t AH /WE t DS t DH t DS t DH DIN valid valid Flaxer Eli - Process Control Ch 4 - 11 JAL RAM Summary SRAM: ● Fast Small systems ● Simple Interface or ● Moderate bit density (4 gates → 4 to 6 very fast transistors) applications ● Moderate cost/bit (cache memory) DRAM (Dynamic RAM): ● moderate speed Large Memories: ● complex interface PC’s ● High bit density (1 transistor cell) Mainframes ● Low cost/bit Flaxer Eli - Process Control Ch 4 - 12 JAL